GPU/Internal Registers: Difference between revisions
Steveice10 (talk | contribs) |
Steveice10 (talk | contribs) |
||
Line 7,509: | Line 7,509: | ||
|} | |} | ||
== | == Shader registers == | ||
=== | === GPUREG_''SH''_BOOLUNIFORM === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,518: | Line 7,518: | ||
|- | |- | ||
| 0 | | 0 | ||
| unsigned, | | unsigned, Boolean register b0 value (0 = false, 1 = true) | ||
|- | |- | ||
| 1 | | 1 | ||
| unsigned, | | unsigned, Boolean register b1 value (0 = false, 1 = true) | ||
|- | |- | ||
| 2 | | 2 | ||
| unsigned, | | unsigned, Boolean register b2 value (0 = false, 1 = true) | ||
|- | |- | ||
| 3 | | 3 | ||
| unsigned, | | unsigned, Boolean register b3 value (0 = false, 1 = true) | ||
|- | |- | ||
| 4 | | 4 | ||
| unsigned, | | unsigned, Boolean register b4 value (0 = false, 1 = true) | ||
|- | |- | ||
| 5 | | 5 | ||
| unsigned, | | unsigned, Boolean register b5 value (0 = false, 1 = true) | ||
|- | |- | ||
| 6 | | 6 | ||
| unsigned, | | unsigned, Boolean register b6 value (0 = false, 1 = true) | ||
|- | |- | ||
| 7 | | 7 | ||
| unsigned, | | unsigned, Boolean register b7 value (0 = false, 1 = true) | ||
|- | |- | ||
| 8 | | 8 | ||
| unsigned, | | unsigned, Boolean register b8 value (0 = false, 1 = true) | ||
|- | |- | ||
| 9 | | 9 | ||
| unsigned, | | unsigned, Boolean register b9 value (0 = false, 1 = true) | ||
|- | |- | ||
| 10 | | 10 | ||
| unsigned, | | unsigned, Boolean register b10 value (0 = false, 1 = true) | ||
|- | |- | ||
| 11 | | 11 | ||
| unsigned, | | unsigned, Boolean register b11 value (0 = false, 1 = true) | ||
|- | |- | ||
| 12 | | 12 | ||
| unsigned, | | unsigned, Boolean register b12 value (0 = false, 1 = true) | ||
|- | |- | ||
| 13 | | 13 | ||
| unsigned, | | unsigned, Boolean register b13 value (0 = false, 1 = true) | ||
|- | |- | ||
| 14 | | 14 | ||
| unsigned, | | unsigned, Boolean register b14 value (0 = false, 1 = true) | ||
|- | |- | ||
| 15 | | 15 | ||
| unsigned, | | unsigned, Boolean register b15 value (0 = false, 1 = true) | ||
|- | |- | ||
| 16-31 | | 16-31 | ||
| | | 0x7FFF | ||
|} | |} | ||
This register is used to set | This register is used to set a shader unit's boolean registers. | ||
=== | === GPUREG_''SH''_INTUNIFORM_I''i'' === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,578: | Line 7,578: | ||
|- | |- | ||
| 0-7 | | 0-7 | ||
| unsigned, | | unsigned, Integer register i''i'' X value | ||
|- | |- | ||
| 8-15 | | 8-15 | ||
| unsigned, | | unsigned, Integer register i''i'' Y value | ||
|- | |- | ||
| 16-23 | | 16-23 | ||
| unsigned, | | unsigned, Integer register i''i'' Z value | ||
|- | |- | ||
| 24-31 | | 24-31 | ||
| unsigned, | | unsigned, Integer register i''i'' W value | ||
|} | |} | ||
These registers are used to set a shader unit's integer registers. | |||
=== | === GPUREG_''SH''_INPUTBUFFER_CONFIG === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,598: | Line 7,598: | ||
! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-3 | ||
| unsigned, | | unsigned, Input vertex attributes - 1 | ||
|- | |- | ||
| 8-15 | | 8-15 | ||
| unsigned, | | unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders) | ||
|- | |- | ||
| 16-23 | | 16-23 | ||
| | | 0x0 | ||
|- | |- | ||
| 24-31 | | 24-31 | ||
| unsigned, | | unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders) | ||
|} | |} | ||
This register is used to | This register is used to configure a shader unit's input buffer. | ||
=== | === GPUREG_''SH''_ENTRYPOINT === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,619: | Line 7,619: | ||
! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-15 | ||
| unsigned, | | unsigned, Code entry point offset, in 32-bit words | ||
|- | |- | ||
| 16-31 | |||
| 0x7FFF | |||
| 16 | |||
| | |||
|} | |} | ||
This register | This register sets a shader unit's code entry point. | ||
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader. | |||
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. | |||
=== | === GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,696: | Line 7,639: | ||
|- | |- | ||
| 0-3 | | 0-3 | ||
| unsigned, | | unsigned, Vertex attribute 0 input register index | ||
|- | |- | ||
| 4-7 | | 4-7 | ||
| unsigned, | | unsigned, Vertex attribute 1 input register index | ||
|- | |- | ||
| 8-11 | | 8-11 | ||
| unsigned, | | unsigned, Vertex attribute 2 input register index | ||
|- | |- | ||
| 12-15 | | 12-15 | ||
| unsigned, | | unsigned, Vertex attribute 3 input register index | ||
|- | |- | ||
| 16-19 | | 16-19 | ||
| unsigned, | | unsigned, Vertex attribute 4 input register index | ||
|- | |- | ||
| 20-23 | | 20-23 | ||
| unsigned, | | unsigned, Vertex attribute 5 input register index | ||
|- | |- | ||
| 24-27 | | 24-27 | ||
| unsigned, | | unsigned, Vertex attribute 6 input register index | ||
|- | |- | ||
| 28-31 | | 28-31 | ||
| unsigned, | | unsigned, Vertex attribute 7 input register index | ||
|} | |} | ||
This register sets the | This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute. | ||
For example, having bits 0-3 set to 5 means that, in the | |||
=== | === GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,730: | Line 7,672: | ||
|- | |- | ||
| 0-3 | | 0-3 | ||
| unsigned, | | unsigned, Vertex attribute 8 input register index | ||
|- | |- | ||
| 4-7 | | 4-7 | ||
| unsigned, | | unsigned, Vertex attribute 9 input register index | ||
|- | |- | ||
| 8-11 | | 8-11 | ||
| unsigned, | | unsigned, Vertex attribute 10 input register index | ||
|- | |- | ||
| 12-15 | | 12-15 | ||
| unsigned, | | unsigned, Vertex attribute 11 input register index | ||
|- | |- | ||
| 16-19 | | 16-19 | ||
| unsigned, | | unsigned, Vertex attribute 12 input register index | ||
|- | |- | ||
| 20-23 | | 20-23 | ||
| unsigned, | | unsigned, Vertex attribute 13 input register index | ||
|- | |- | ||
| 24-27 | | 24-27 | ||
| unsigned, | | unsigned, Vertex attribute 14 input register index | ||
|- | |- | ||
| 28-31 | | 28-31 | ||
| unsigned, | | unsigned, Vertex attribute 15 input register index | ||
|} | |} | ||
This register sets the | This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute. | ||
For example, having bits 0-3 set to 5 means that, in the | |||
=== | === GPUREG_''SH''_OUTMAP_MASK === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,764: | Line 7,705: | ||
|- | |- | ||
| 0 | | 0 | ||
| unsigned, | | unsigned, Output register o0 enabled (0 = disabled, 1 = enabled) | ||
|- | |- | ||
| 1 | | 1 | ||
| unsigned, | | unsigned, Output register o1 enabled (0 = disabled, 1 = enabled) | ||
|- | |- | ||
| 2 | | 2 | ||
| unsigned, | | unsigned, Output register o2 enabled (0 = disabled, 1 = enabled) | ||
|- | |- | ||
| 3 | | 3 | ||
| unsigned, | | unsigned, Output register o3 enabled (0 = disabled, 1 = enabled) | ||
|- | |- | ||
| 4 | | 4 | ||
| unsigned, | | unsigned, Output register o4 enabled (0 = disabled, 1 = enabled) | ||
|- | |- | ||
| 5 | | 5 | ||
| unsigned, | | unsigned, Output register o5 enabled (0 = disabled, 1 = enabled) | ||
|- | |- | ||
| 6 | | 6 | ||
| unsigned, | | unsigned, Output register o6 enabled (0 = disabled, 1 = enabled) | ||
|- | |||
| 7 | |||
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 8 | |||
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 9 | |||
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 10 | |||
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 11 | |||
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 12 | |||
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 13 | |||
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 14 | |||
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 15 | |||
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only) | |||
|- | |||
| 16-31 | |||
| 0x0 | |||
|} | |} | ||
This register toggles | This register toggles a shader unit's output registers. | ||
=== | === GPUREG_''SH''_CODETRANSFER_END === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,793: | Line 7,764: | ||
! Description | ! Description | ||
|- | |- | ||
| 0 | | 0-31 | ||
| unsigned, | | unsigned, Signal transfer end (0 = idle, non-zero = signal) | ||
|} | |} | ||
This register's value should be set to 1 in order to finalize the transfer of | This register's value should be set to 1 in order to finalize the transfer of shader code. | ||
=== | === GPUREG_''SH''_FLOATUNIFORM_INDEX === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,805: | Line 7,776: | ||
! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-7 | ||
| unsigned, Target | | unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95) | ||
|- | |- | ||
| 31 | | 31 | ||
| unsigned, | | unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23) | ||
|} | |} | ||
This register sets the target | This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory. | ||
=== | === GPUREG_''SH''_FLOATUNIFORM_DATA''i'' === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,821: | Line 7,792: | ||
|- | |- | ||
| 0-31 | | 0-31 | ||
| | | Floating-point register component data | ||
|} | |} | ||
This register is used to set the | This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. | ||
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes : | * In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes: | ||
** first word : ZZWWWWWW | ** first word : ZZWWWWWW | ||
** second word : YYYYZZZZ | ** second word : YYYYZZZZ | ||
Line 7,832: | Line 7,803: | ||
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order. | * In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order. | ||
=== | === GPUREG_''SH''_CODETRANSFER_INDEX === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,839: | Line 7,810: | ||
|- | |- | ||
| 0-11 | | 0-11 | ||
| unsigned, Target | | unsigned, Target shader code offset | ||
|} | |} | ||
This register is used to set the offset at which upcoming | This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written. | ||
=== | === GPUREG_''SH''_CODETRANSFER_DATA''i'' === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,853: | Line 7,822: | ||
|- | |- | ||
| 0-31 | | 0-31 | ||
| unsigned, | | unsigned, Shader instruction data | ||
|} | |} | ||
This register is used to transfer | This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register. | ||
=== | === GPUREG_''SH''_OPDESCS_INDEX === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,864: | Line 7,833: | ||
! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-11 | ||
| unsigned, Target | | unsigned, Target shader operand descriptor offset | ||
|} | |} | ||
This register is used to set the offset at which upcoming | This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written. | ||
=== | === GPUREG_''SH''_OPDESCS_DATA''i'' === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 7,877: | Line 7,846: | ||
|- | |- | ||
| 0-31 | | 0-31 | ||
| unsigned, | | unsigned, Shader operand descriptor data | ||
|} | |} | ||
This register is used to transfer | This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register. | ||
== Vertex shader registers == | == Vertex shader registers == |