GPU/External Registers: Difference between revisions
Documented some timing and display registers |
→Map: mentions that internal registers are exposed here |
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| [[#Transfer_Engine|Transfer Engine]] "DMA" | | [[#Transfer_Engine|Transfer Engine]] "DMA" | ||
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|colspan="5"| 0x1EF01000/0x10401000 - 0x1EF01C00/0x10401C00 maps to [[GPU/Internal_Registers|GPU internal registers]]. These registers are usually not read/written directly here, but are written using the command list interface below (corresponding to the GPUREG_CMDBUF_* internal registers) | |||
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| 0x1EF01000 | | 0x1EF01000 | ||