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2,456 bytes added ,  22:59, 24 May 2020
Fix ARM7 AGB-related info
| <code>u16</code>
| <code>0x10018104</code>
| <code>ARM7_?_CNTARM7_SAVE_MEMORY_CNT</code>
| 2
|-
| <code>u16</code>
| <code>0x10018108</code>
| <code>ARM7_RTC_CNT?</code>
| 2
|-
| <code>u32</code>
| <code>0x10018110</code>
| <code>ARM7_RTC_VAL_LOARM7_RTC_VAL_DATE</code>
| 4
|-
| <code>u32</code>
| <code>0x10018114</code>
| <code>ARM7_RTC_VAL_HIARM7_RTC_VAL_TIME</code>
| 4
|-
| <code>u32</code>
| <code>0x10018118</code>
| <code>ARM7_RTC_LO?ARM7_RTC_VAL_SETTINGS</code>
| 4
|-
| <code>u32</code>
| <code>0x1001811C</code>
| <code>ARM7_RTC_HI?ARM7_RTC_VAL_ADJUST</code>
| 4
|-
| <code>arm7_save_cfg_tu32</code>
| <code>0x10018120</code>
| <code>ARM7_SAVE_CFGARM7_SAVE_FLASH_CHIP_ERASE_CYCLES</code>| 164|-| <code>u32</code>| <code>0x10018124</code>| <code>ARM7_SAVE_FLASH_SECTOR_ERASE_CYCLES</code>| 4|-| <code>u32</code>| <code>0x10018128</code>| <code>ARM7_SAVE_FLASH_PROGRAM_CYCLES</code>| 4|-| <code>u32</code>| <code>0x1001812C</code>| <code>ARM7_SAVE_EEPROM_WRITE_CYCLES</code>| 4
|}
===ARM7_SAVE_MODE===
This tells the save storage emulation hardware which device type to emulate (64k EEPROM, a 512k Flash chip model, and SRAM are all that have been used officially; several other 512k Flash chip models, two 1 Mbit Flash chip models and 8k 4k EEPROM are also supported). This comes directly from the [[3DS_Virtual_Console#Footer|ROM footer]]. ===ARM7_SAVE_MEMORY_CNT===This register controls whether the GBA save memory region located at <code>0x08080000</code> is accessible to ARM9 or to the ARM7 (via the emulated save chip). When it's set to 0x0 ARM7 has access, while ARM9 has access when it's set to 0x1. ===ARM7_RTC_CNT===This register controls the emulated RTC hardware and access to some of its registers.To set or read the data from ARM7_RTC_VAL_SETTINGS or ARM7_RTC_VAL_ADJUST, first <code>ARM7_RTC_CNT</code>'s bit 15 is waited on. Next <code>ARM7_RTC_CNT</code> is set to zero.  For a write: the two registers are written, a 1 is written to <code>ARM7_RTC_CNT</code>, and it is waited on the same as before. Afterwards if bit 14 is not set in <code>ARM7_RTC_CNT</code>, the value was set successfully. This also starts the emulated RTC. For a read: a 2 is written to <code>ARM7_RTC_CNT</code>, it's waited on again. Afterwards, if bit 14 is not set, the aforementioned registers can be read. Presumably the hardware can be re-enabled by writing a zero to <code>ARM7_RTC_CNT</code> at this point, but <code>AGB_FIRM</code> does not.
===ARM7_RTC_VALARM7_RTC_VAL_DATE / ARM7_RTC_VAL_TIME===These registers are set to the current LgyP9 date+time before ARM7_RTC_CNT/ARM7_RTC_? the other RTC-related registers are used.
They contain the following structure, set up on the stack then both u32 registers are written one after the other:
s8 second_bcd;
===ARM7_RTC ''?''ARM7_RTC_VAL_SETTINGS===These registers may be used This register appears to contain the emulated RTC chip's configuration (accessible via the "control a " register on realhardware), containing settings like 12/24-time clockhour mode. To set or read the data here, first Access is controlled by <code>ARM7_RTC_CNT</code>(see above). ===ARM7_RTC_VAL_ADJUST===This register appears to contain the emulated RTC chip's bit 15 time difference, relative to <code>ARM7_RTC_VAL_DATE</code> / <code>ARM7_RTC_VAL TIME</code>, in seconds. Access is waited on. Next controlled by <code>ARM7_RTC_CNT</code> (see above). ===ARM7_SAVE_FLASH_CHIP_ERASE_CYCLES===This register seems to configure the emulated Flash chip to take a specified amount of time to complete a chip erase operation (relative to the DS' ARM7/bus speed). Two variations exist in officially released games, one meant for 512k Flash chips and one for 1 Mbit Flash chips. It is set to zerocopied from from rom footer + <code>0x10</code>.
For ===ARM7_SAVE_FLASH_SECTOR_ERASE_CYCLES===This register seems to configure the emulated Flash chip to take a write: the two registers are written, specified amount of time to complete a 1 is written sector erase operation (relative to <code>ARM7_RTC_CNT<the DS' ARM7/code>bus speed). Two variations exist in officially released games, one meant for 512k Flash chips and it is waited on the same as beforeone for 1 Mbit Flash chips. Afterwards if bit 14 It is not set in copied from from rom footer + <code>ARM7_RTC_CNT0x14</code>, the value was set successfully.
For ===ARM7_SAVE_FLASH_PROGRAM_CYCLES===This register seems to configure the emulated Flash chip to take a read: specified amount of time to complete a 2 is written program operation (relative to <code>ARM7_RTC_CNT<the DS' ARM7/code>bus speed). Two variations exist in officially released games, it's waited on againone meant for 512k Flash chips and one for 1 Mbit Flash chips. Afterwards, if bit 14 It is not set, the RTC can be read. Presumably the hardware can be re-enabled by writing a zero to <code>ARM7_RTC_CNT</code> at this point, but copied from from rom footer + <code>AGB_FIRM0x18</code> does not.
===ARM7_SAVE_CFGARM7_SAVE_EEPROM_WRITE_CYCLES===This register seems to configure the emulated EEPROM chip to take a specified amount of time to complete a write operation (relative to the DS' ARM7/bus speed). Two variations exist in officially released games, one meant for 64k EEPROM chips and one for 4k EEPROM chips. It is copied from from rom footer + <code>0x100x1C</code>. It presumably configures details about storage, such as IDs, and likely allows enabling the RTC for games which need it. Format of this data is unknown, and slightly difficult to determine without some hardware poking.
==Memory map==
* <code>0x08060000</code> → <code>0x03800000</code>, ARM7 WRAM (64KiB)
* <code>0x080B0000</code> → <code>0x03000000</code>, GBA IWRAM (32KiB)
* <code>0x08080000</code> → EEPROM/SRAM/Flash 512k/Flash 1Mbit (the 2 512k banks are contiguous in memory). Appears to be mirrored at Access is controlled by <code>0x080C0000ARM7_SAVE_MEMORY_CNT</code>, maybe first mapping is read-only and second is writable? (see above). <code>0x100181040x080C0000</code> must be set holds a mirror which is used by LgyP9 on boot to 1 read the SD savedata before reading memory herethe mode switch, and restored to its previous value afterwardsthe data is then copied.
* <code>0x01FFC000</code> → <code>0x01000000</code>, ARM9 ITCM under TWL (16KiB)

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