Changes

Jump to navigation Jump to search
1,750 bytes added ,  04:12, 11 December 2015
m
=unk Interrupt info=The unk Interrupt info structure is located at sharedmemvadr + threadindexprocess_gsp_index*0x40.
It is a list of interrupts (id's 0-6 exist).
{| class="wikitable" border="1"
! Description
|-
| 00x0| index Index of the next last processed data (field size is 0x33) (must be updated manually)|-| 0x1| To be processed datafields, (max 0x300x20 for PDC interrupts else the missed PDC filds are used,max 0x34 for all other if more interrupts happen and the Errorflag is 0 the Errorflag is set to 1) |-| 0x2| Errorflag (fild size if the first bit of Errorflag is 0x33set future PDC interrupts are ignored)|-| 0x3| not used
|-
| 10x4-0x7| to be processed datafildsmissed PDC0
|-
| 0x20x8-0xC0xB| unkmissed PDC1
|-
| 0xC-0x3F
| u8 datafild[0x33]Interrupttypefield (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop (sent to all threads), 3=PDC1/VBlankBottom (sent to all threads), 4=PPF, 5=P3D, 6=DMA)
|}
=Command Buffer Header=
 
The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.
 
{| class="wikitable" border="1"
|-
| u32 Error code for the last GX command which failed
|}
 
The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.
=Command Header=
=Commands=
==GX RequestDmaTrigger DMA Request ==
{| class="wikitable" border="1"
|-
|-
| 7
| Flag: when Flush source buffer is not located in VRAM and this flag is non-zero(0 = don't flush, svcFlushProcessDataCache is used with the source buffer.1 = flush)
|}
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer.
==GX SetCommandList LastTrigger Command List Processing ==
{| class="wikitable" border="1"
|-
|-
| 3
| FlagUpdate gas additive blend results (0 = don't update, bit0 is written to GSP module state1 = update)
|-
| 6-4
|-
| 7
| When non-zeroFlush buffer (0 = don't flush, call svcFlushProcessDataCache(1 = flush) with the specified buffer
|}
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU_CommandsGPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.
==GX SetMemoryFillTrigger Memory Fill ==
{| class="wikitable" border="1"
|-
|-
| 1
| Buf0 start address(0 = don't fill anything)
|-
| 2
|-
| 4
| Buf1 start address(0 = don't fill anything)
|-
| 5
|-
| 7
| The low u16 is width0, while the high u16 is width1 Control0 <nowiki>|</nowiki> (?Control1 << 16)
|}
This commands command converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters. ==GX SetDisplayTransferTrigger Display Transfer ==
{| class="wikitable" border="1"
|-
|}
This command converts the specified addresses to physical addresses, then writes these physical addresses and parameters to the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM. Note that unlike the LCD framebuffers, the GPU framebuffer seems to use fixed-point/floats for the color format.
The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers. Display transfers are performed asynchronously, so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data. Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly. ==GX SetTextureCopyTrigger Texture Copy ==
{| class="wikitable" border="1"
|-
|-
| 1
| Input buffer address.
|-
| 2
| Output buffer address.
|-
| 3
| SizeTotal bytes to copy, not including gaps.
|-
| 4
| Input [[GPU|dimensions]]?Bits 0-15: Size of input line, in bytes. Bits 16-31: Gap between input lines, in bytes.
|-
| 5
| Output dimensions?Same as 4, but for the output.
|-
| 6
| Flags, normally this corresponding to the [[GPU/External_Registers#Transfer_Engine|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is 0x8always set, with bit2 optionally bit 2 is set when either of if any output dimension is smaller than the dimensions fields input, and other bits are setalways 0.
|-
| 7
|}
This command is similar to cmd3, this command . It also writes to triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]] registers at 0x1EF00C00, but setting the TextureCopy parameters.
==GX SetCommandList First Flush Cache Regions ==
{| class="wikitable" border="1"
|-
1,291

edits

Navigation menu