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GPU/External Registers: Difference between revisions

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m Add to GPU category
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Update DisplayTransfer control bits
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| 3
| 3
| When set, the input framebuffer data is copied as-is to the output framebuffer, without any kind of conversions. The data is truncated to the output size.
| Uses a TextureCopy mode transfer. All other bits in this register seem to be ignored when this is set.
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| 4
| 4
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| 5
| 5
| Writable, but purpose unknown (usually zero)
| Don't perform tiled-linear conversion. Incompatible with bit 1, so only tiled-tiled transfers can be done, not linear-linear.
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| 7-6
| 7-6
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| 16
| 16
| Unknown, normally zero.
| Use some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
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| 17-23
| 17-23
| Not writable
| Not writable
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| 24
| 24-25
| Scale down the input image to its half width using a box filter.
| Scale down the input image using a box filter. 0 = No downscale, 1 = 2x1 downscale. 2 = 2x2 downscale, 3 = invalid
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| 25
| Scale down the input image to its half height and half width using a box filter.
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| 31-26
| 31-26
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