DSP Binary: Difference between revisions
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| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are ( | | Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[http://www.3dbrew.org/wiki/PDN_Registers#PDN_SHAREDWRAM_32K_DATA|PDN_SHAREDWRAM_32K_DATA]] and [[http://www.3dbrew.org/wiki/PDN_Registers#PDN_SHAREDWRAM_32K_CODE|PDN_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000). | ||
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| 0x10C | | 0x10C | ||