SHA Registers: Difference between revisions
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| style="background: green" | Yes | | style="background: green" | Yes | ||
| [[# | | [[#SHA_FIFO|SHA_FIFO]] | ||
| 0x1000A080 | | 0x1000A080 | ||
| 0x40 | | 0x40 | ||
| Line 37: | Line 37: | ||
! Description | ! Description | ||
|- | |- | ||
| 0-1 | | 0 | ||
| | | Start (1=enable/busy, 0=idle) | ||
|- | |||
| 1 | |||
| Final round (1=enable/busy, 0=normal) | |||
|- | |- | ||
| 2 | | 2 | ||
| | | Input DMA enable (1= enable, 0=disable) | ||
|- | |- | ||
| 3 | | 3 | ||
| Output Endianess (0= | | Output Endianess (0=little, 1=big) | ||
|- | |- | ||
| 4-5 | | 4-5 | ||
| Line 56: | Line 59: | ||
|- | |- | ||
| 8 | | 8 | ||
| | | Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO. | ||
|- | |- | ||
| 9 | | 9 | ||
| | | Enable FIFO (1=fifo, 0=write-only) | ||
|- | |- | ||
| 10 | | 10 | ||
| | | Output DMA enable (1= enable, 0=disable) | ||
|- | |- | ||
| 16 | | 16 | ||
| | | ? | ||
|- | |- | ||
| 17 | | 17 | ||
| | | ? | ||
|} | |} | ||
Bit 8 is used when boot9 chains eMMC reads with AES and SHA to to load, decrypt and verify FIRM partitions. | |||
== SHA_BLKCNT == | == SHA_BLKCNT == | ||
| Line 77: | Line 82: | ||
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register. | This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register. | ||
== | == SHA_FIFO == | ||
The data to be hashed must be written here. | The data to be hashed must be written here. It does not matter what offset is written to. | ||