SHA Registers: Difference between revisions

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== Registers ==
= Registers =
{| class="wikitable" border="1"
{| class="wikitable" border="1"
NAME
Old3DS
PHYSICAL ADDRESS
Name
WIDTH
Address
!  Width
!  Used by
|-
|-
| REG_SHA_CNT
| style="background: green" | Yes
| [[#SHA_CNT|SHA_CNT]]
| 0x1000A000
| 0x1000A000
| 4
| 4
| Boot9, Process9
|-
|-
| REG_SHA_DATASIZE
| style="background: green" | Yes
| [[#SHA_BLKCNT|SHA_BLKCNT]]
| 0x1000A004
| 0x1000A004
| 4
| 4
| Process9
|-
|-
| REG_SHA_OUT
| style="background: green" | Yes
| [[#SHA_HASH|SHA_HASH]]
| 0x1000A040
| 0x1000A040
| 0x20
| 0x20
| Process9
|-
|-
| REG_SHA_IN
| style="background: green" | Yes
| [[#SHA_FIFO|SHA_FIFO]]
| 0x1000A080
| 0x1000A080
| 0x40
| 0x40
| Boot9, Process9
|}
|}


 
== SHA_CNT ==
== REG_SHA_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-1
| 0
| 0=Hash ready, 1=Normal, 2=Final Round
| Start (1=enable/busy, 0=idle)
|-
| 1
| Final round (1=enable/busy, 0=normal)
|-
| 2
| Input DMA enable (1= enable, 0=disable)
|-
| 3
| Output Endianess (0=little, 1=big)
|-
| 4-5
| Mode (0=SHA256, 1=SHA224, 2=3=SHA1)
|-
| 6
| ?
|-
| 7
| ?
|-
|-
|3
| 8
| Endianess (0=Little endian, 1=Big endian)
| Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO.
|-
|-
|4
| 9
| ?  Input related. Changes the hash completely
| Enable FIFO (1=fifo, 0=write-only)
|-
|-
|5
| 10
| Mode (0=SHA256, 1=SHA1)
| Output DMA enable (1= enable, 0=disable)
|-
|-
| 16
| 16
| Enable
| ?
|-
|-
| 17
| 17
| 1 when FIFO expects read/write
| ?
|}
|}


Bit 8 is used when boot9 chains eMMC reads with AES and SHA to to load, decrypt and verify FIRM partitions.


== REG_SHA_DATASIZE ==
== SHA_BLKCNT ==
This reg contains the total size of the data written to REG_SHA_IN.
This reg contains the total size of the data written to REG_SHA_IN, this field is updated when performing hash-function final-round.


== REG_SHA_OUT ==
== SHA_HASH ==
This reg contains the SHA* hash after the final round.
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.


== REG_SHA_IN ==
== SHA_FIFO ==
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).
The data to be hashed must be written here. It does not matter what offset is written to.