GPU/External Registers: Difference between revisions
| Line 277: | Line 277: | ||
| Framebuffer format | | Framebuffer format | ||
| Bit0-15: framebuffer format, bit16-31: unknown | | Bit0-15: framebuffer format, bit16-31: unknown | ||
|- | |||
| 0x74 | |||
| PDC control | |||
| Bit 0: Enable display controller. | |||
Bit 8: H(Blank?) IRQ mask (0 = enabled). | |||
Bit 9: VBlank IRQ mask (0 = enabled). | |||
Bit 10: Error IRQ mask? (0 = enabled). | |||
Bit 16: Output enable? | |||
|- | |- | ||
| 0x78 | | 0x78 | ||
| Framebuffer select | | Framebuffer select and status | ||
| | | Bit 0: Next framebuffer to display (after VBlank). | ||
Bit 4: Currently displaying framebuffer? | |||
Bit 8: Reset FIFO? | |||
Bit 16: H(Blank?) IRQ status/ack. Write 1 to aknowledge. | |||
Bit 17: VBlank IRQ status/ack. | |||
Bit 18: Error IRQ status/ack? | |||
|- | |- | ||
| 0x80 | | 0x80 | ||