DSP Binary: Difference between revisions

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~~[[Category:File formats]]~~

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! Offset

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| 0x108

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| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[~~http://www.3dbrew.org/wiki/PDN_Registers~~#~~PDN_SHAREDWRAM_32K_DATA~~|~~PDN_SHAREDWRAM_32K_DATA~~]] and [[~~http://www.3dbrew.org/wiki/PDN_Registers~~#~~PDN_SHAREDWRAM_32K_CODE~~|~~PDN_SHAREDWRAM_32K_CODE~~]], located at physical address 0x10140000 (mapped to 0x1EC40000).

| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]] and [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).

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| 0x10C

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| 0x10F

| 1

| Flags (bit0=?, bit1=load special segment)

| Flags:

bit0: if set, DSP module calls [[DSP:RecvData]] on all three registers and expects them to reply value 1

bit1: if set, load special segment

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| 0x110

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The normal ending of this files is *.cdc

[[Category:File formats]]

[[Category:DSP]]

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-[[Category:File formats]]
 {| class="wikitable" border="1"
 !  Offset
@@ Line 20: / Line 18: @@
 | 0x108
 | 2
-| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[http://www.3dbrew.org/wiki/PDN_Registers#PDN_SHAREDWRAM_32K_DATA|PDN_SHAREDWRAM_32K_DATA]] and [[http://www.3dbrew.org/wiki/PDN_Registers#PDN_SHAREDWRAM_32K_CODE|PDN_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).
+| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]] and [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).
 |-
 | 0x10C
@@ Line 36: / Line 34: @@
 | 0x10F
 | 1
-| Flags (bit0=?, bit1=load special segment)
+| Flags:
+bit0: if set, DSP module calls [[DSP:RecvData]] on all three registers and expects them to reply value 1
+bit1: if set, load special segment
 |-
 | 0x110
@@ Line 86: / Line 88: @@
 The normal ending of this files is *.cdc
+[[Category:File formats]]
+[[Category:DSP]]