SPICARD Registers: Difference between revisions

← Older edit

@@ Line 5: / Line 5: @@
 !  Address
 !  Width
+!  RW
 !  Used by
 |-
 | style="background: green" | Yes
-| [[#REG_SPICARDCNT|REG_SPICARDCNT]]
+| [[#NSPI_CNT|NSPI_CNT]]
 | 0x1000D800
 | 4
+| RW
 |
 |-
 | style="background: green" | Yes
-| [[#REG_SPICARDASSERT|REG_SPICARDASSERT]]
+| [[#NSPI_DONE|NSPI_DONE]]
 | 0x1000D804
 | 4
+| RW
 |
 |-
 | style="background: green" | Yes
-| [[#REG_SPICARDSIZE|REG_SPICARDSIZE]]
+| [[#NSPI_BLKLEN|NSPI_BLKLEN]]
 | 0x1000D808
 | 4
+| RW
 |
 |-
 | style="background: green" | Yes
-| [[#REG_SPICARDFIFO|REG_SPICARDFIFO]]
+| [[#NSPI_FIFO|NSPI_FIFO]]
 | 0x1000D80C
 | 4
+| RW
 |
 |-
 | style="background: green" | Yes
-| [[#REG_SPICARDFIFOSTAT|REG_SPICARDFIFOSTAT]]
+| [[#NSPI_STATUS|NSPI_STATUS]]
 | 0x1000D810
 | 4
+| R
 |
 |-
 | style="background: green" | Yes
-| ?
+| [[#NSPI_AUTOPOLL|NSPI_AUTOPOLL]]
 | 0x1000D814
 | 4
+| RW
 |
 |-
 | style="background: green" | Yes
-| ?
+| [[#NSPI_INT_MASK|NSPI_INT_MASK]]
 | 0x1000D818
 | 4
+| W?
 |
 |-
 | style="background: green" | Yes
-| ?
+| [[#NSPI_INT_STAT|NSPI_INT_STAT]]
 | 0x1000D81C
 | 4
+| RW
 |
 |}
-== REG_SPICARDCNT ==
+== NSPI_CNT ==
 {| class="wikitable" border="1"
 !  BIT
 !  DESCRIPTION
 |-
-| 2-0
+| 0-2
 | [[Filesystem_services#CardSpiBaudRate|Baud Rate]]
 |-
@@ Line 77: / Line 86: @@
 |}
-This register seems to have a bug where the lower 8 bits are shifted up by 16 when reading them back.
+This register seems to have a bug where the lower 8 bits are shifted up by 16 when reading this register.
-== REG_SPICARDASSERT ==
+== NSPI_DONE ==
-When deasserting the card, this registers is set to 0. Presumably contains 1 when the card is asserted.
+Contains 1 when the SPI slave is selected. A 0 is written here on transfer end to deselect the slave.
-== REG_SPICARDSIZE ==
+== NSPI_BLKLEN ==
 {| class="wikitable" border="1"
 !  BIT
 !  DESCRIPTION
 |-
-| 31-0
+| 0-20
 | Transfer size
+|-
+| 21-31
+| Unused
 |}
-== REG_SPICARDFIFO ==
+== NSPI_FIFO ==
 {| class="wikitable" border="1"
 !  BIT
 !  DESCRIPTION
 |-
-| 31-0
+| 0-31
 | Data
 |}
-== REG_SPICARDFIFOSTAT ==
+This FIFO is one way (half-duplex).
+== NSPI_STATUS ==
 {| class="wikitable" border="1"
 !  BIT
@@ Line 108: / Line 122: @@
 | FIFO Full (0 = not full, 1 = full)
 |}
+== NSPI_AUTOPOLL ==
+{| class="wikitable" border="1"
+!  BIT
+!  DESCRIPTION
+|-
+| 0-7
+| Command
+|-
+| 16-19
+| Timeout (Tries = 31<<Baudrate (from NSPI_CNT) + Timeout)
+|-
+| 24-26
+| Bit offset (0-7)
+|-
+| 30
+| Poll for a set or unset bit
+|-
+| 31
+| 1 = Enable/Busy
+|}
+This automatically sends a command to the device and compares the specified bit in the response with bit 30 until it matches or a timeout occurs. Nintendo uses a timeout of 10 which roughly equals 1 second. This is used in Process9 to poll the gamecard SPI flash status register for write operation finished or write enable.
+== NSPI_INT_MASK ==
+{| class="wikitable" border="1"
+!  BIT
+!  DESCRIPTION
+|-
+| 0
+| Transfer finished (1 = disabled)
+|-
+| 1
+| Autopoll success (1 = disabled)
+|-
+| 2
+| Autopoll timeout (1 = disabled)
+|}
+== NSPI_INT_STAT ==
+{| class="wikitable" border="1"
+!  BIT
+!  DESCRIPTION
+|-
+| 0
+| Transfer finished (also fires on each autopoll try?)
+|-
+| 1
+| Autopoll success
+|-
+| 2
+| Autopoll timeout
+|}
+[[IRQ_Registers|Interrupt]] ID 23 is fired when any of the bits change to 1 except for interrupts masked in [[#NSPI_INT_MASK|NSPI_INT_MASK]]. Writing 1 to a bit in this register aknowledges the interrupt.