SPI Registers: Difference between revisions
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32-bit FIFO for reading/writing the SPI payload. | 32-bit FIFO for reading/writing the SPI payload. This FIFO is one way (half-duplex). | ||
== NSPI_STATUS == | == NSPI_STATUS == | ||
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| 16-19 | | 16-19 | ||
| Timeout (Tries = 31<< | | Timeout (Tries = 31<<Clock (from [[#NSPI_CNT|NSPI_CNT]]) + Timeout) | ||
|- | |- | ||
| 24-26 | | 24-26 | ||
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| 0 | | 0 | ||
| Transfer finished | | Transfer finished (1 = disabled) | ||
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| 1 | | 1 | ||
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| 0 | | 0 | ||
| Transfer finished? | | Transfer finished (also fires on each autopoll try?) | ||
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| 1 | | 1 | ||
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[[ARM11_Interrupts#Hardware_Interrupts|Interrupt]] ID 0x56 or 0x57 (depending on the bus) is fired when any of the bits change to 1 except for interrupts masked in [[#NSPI_INT_MASK|NSPI_INT_MASK]]. Writing 1 to a bit in this register aknowledges the interrupt. | [[ARM11_Interrupts#Hardware_Interrupts|Interrupt]] ID 0x24, 0x56 or 0x57 (depending on the bus) is fired when any of the bits change to 1 except for interrupts masked in [[#NSPI_INT_MASK|NSPI_INT_MASK]]. Writing 1 to a bit in this register aknowledges the interrupt. | ||