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I2S Registers: Difference between revisions

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== Registers ==
= Registers =
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  NAME
!  Old3DS
!  PHYSICAL ADDRESS
!  Name
!  ARM11 PROCESS ADDRESS
!  Address
!  WIDTH
!  Width
!  Used by
|-
|-
| ?
| style="background: green" | Yes
| 0x10141114
| [[#I2S1_CNT|I2S1_CNT]]
| 0x1EC41114
| 0x10145000
| 2
| 2
| Codec sysmodule, AgbBg, TwlBg
|-
|-
| ?
| style="background: green" | Yes
| 0x10141116
| [[#I2S2_CNT|I2S2_CNT]]
| 0x1EC41116
| 0x10145002
| 2
| 2
| Codec sysmodule, AgbBg, TwlBg
|}
|}


==0x1EC41114 and 0x1EC41116==
 
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.
==I2S1_CNT==
{| class="wikitable" border="1"
!  Bit
!  Description
|-
| 0-5
| DSP volume (doesn't affect csnd).
|-
| 6-11
| GBA hardware master volume. And DSi too?
|-
| 12
| Unknown purpose. Maybe direction for microphone input?
|-
| 13
| I2S frequency. 0=32.728498046875 kHz, 1=47.605088068181818181818 kHz.
|-
| 14
| First MCLK output. 0=8.3784955 MHz, 1=16.756991 MHz.
|-
| 15
| Enable (0=Disabled, 1=Enabled)
|}
 
This I2S line is used the DSP, GBA hardware and microphone.
 
This is usually set to 0xC800 or 0xC820 when the DSP is active.
 
 
==I2S2_CNT==
{| class="wikitable" border="1"
!  Bit
!  Description
|-
| 0-12
| Unused (0).
|-
| 13
| I2S frequency. 0=32.728498046875 kHz, 1=47.605088068181818181818 kHz.
|-
| 14
| Second MCLK output. Connected to the CODEC chip. 0=8.3784955 MHz, 1=16.756991 MHz.
|-
| 15
| Enable (0=Disabled, 1=Enabled)
|}
 
This I2S line is used by CSND.
 
Usually set to 0xE000.
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