Memory layout: Difference between revisions
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==0x17E10000== | |||
The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. | |||
=ARM9 Physical memory regions = | =ARM9 Physical memory regions = | ||