CONFIG11 Registers: Difference between revisions
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== | == PDN_MPCORE_CLKCNT == | ||
This is used for configuring the New3DS ARM11 CPU clock-rate(unknown if writing here does anything on Old3DS). | |||
This is used for configuring the New3DS ARM11 CPU | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
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|- | |- | ||
| 0 | | 0 | ||
| Always set to 1 on both Old3DS and New3DS. | | Always(?) set to 1 on both Old3DS and New3DS. | ||
|} | |||
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of PDN_MPCORE_CFG: | |||
{| class="wikitable" border="1" | |||
! Register value | |||
! Higher-clockrate bit set in svcKernelSetState Param0 | |||
! PDN_MPCORE_CFG bit2 set | |||
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state | |||
! Clock-rate multiplier | |||
! Description | |||
|- | |- | ||
| | | 0x1 | ||
| | | No | ||
| Yes | |||
| 0x1 | |||
| 1x | |||
| 268MHz | |||
|- | |||
| 0x2 | |||
| No | |||
| No | |||
| 0x1 | |||
| 1x | |||
| 268MHz | |||
|- | |||
| 0x5 | |||
| Yes | |||
| Yes | |||
| 0x3 | |||
| 3x | |||
| 804MHz | |||
|- | |||
| 0x3 | |||
| Yes | |||
| No | |||
| 0x2 | |||
| 2x | |||
| 536MHz (tested on New3DS) | |||
|} | |} | ||
Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). | |||
== PDN_MPCORE_CNT == | == PDN_MPCORE_CNT == | ||