I2C Registers: Difference between revisions

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bit0: power off

bit1: full reboot (unused). Discards things like [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]]

bit2: reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.

- Asserts RESET1 via PMIC command (?) (deasserts nRESET1). This could be the reset that controls some CFG9 registers

bit3: reset ~~FCRAM~~ (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also implements this function.

- Asserts RESET2 (P0.1 = 0, PM0.1 = 0 (output)) (deasserts nRESET2)

- Asserts FCRAM_RESET (P3.0 = 0) (deasserts nFCRAM_RESET)

bit2: normal reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.

- Asserts RESET2 (P0.1 = 0, PM0.1 = 0)

- If in NTR emulation mode (see reg 0x02), asserts FCRAM_RESET (P3.0 = 0)

- Resets TWL MCU i2c registers

bit3: FCRAM reset (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also possibly implements this function)

- Asserts FCRAM_RESET (P3.0 = 0)

bit4: signal that sleep mode is about to be entered (used by PTM)

Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.

If any of the reset bits is set, the MCU waits for 5ms, then deasserts RESET1 (via PMIC), RESET2 (PM0.1 = 1 (input)) and FCRAM_RESET (P3.0 = 1), and reinitializes some other various registers after a 100ms delay.

|-

| 0x21

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Line 569:

|-

| 0x3F

| s

| d

| wo

| 2 bits

bit0: ~~turns off P00 and sets~~ it ~~to output mode~~ (seems to kill the entire SoC)

bit0: Asserts RESET1 (P0.0 = 0, PM0.0 = 0 (output)) but does NOT deassert it (wtf?). This seems to kill the entire SoC: is it because it doesn't deassert it, or does it not deassert it because the SoC hangs anyway? This is the pin that controls some security-critical regs like CFG9_BOOTENV!

bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output

|-

@@ Line 409: / Line 409: @@
    bit0: power off
    bit1: full reboot (unused). Discards things like [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]]
-   bit2: reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.
+    - Asserts RESET1 via PMIC command (?) (deasserts nRESET1). This could be the reset that controls some CFG9 registers
-   bit3: reset FCRAM (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also implements this function.
+    - Asserts RESET2 (P0.1 = 0, PM0.1 = 0 (output)) (deasserts nRESET2)
+    - Asserts FCRAM_RESET (P3.0 = 0) (deasserts nFCRAM_RESET)
+   bit2: normal reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.
+    - Asserts RESET2 (P0.1 = 0, PM0.1 = 0)
+    - If in NTR emulation mode (see reg 0x02), asserts FCRAM_RESET (P3.0 = 0)
+    - Resets TWL MCU i2c registers
+   bit3: FCRAM reset (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also possibly implements this function)
+    - Asserts FCRAM_RESET (P3.0 = 0)
    bit4: signal that sleep mode is about to be entered (used by PTM)
 Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
+If any of the reset bits is set, the MCU waits for 5ms, then deasserts RESET1 (via PMIC), RESET2 (PM0.1 = 1 (input)) and FCRAM_RESET (P3.0 = 1), and reinitializes some other various registers after a 100ms delay.
 |-
 | 0x21
@@ Line 560: / Line 569: @@
 |-
 | 0x3F
-| s
+| d
 | wo
 | 2 bits
-   bit0: turns off P00 and sets it to output mode (seems to kill the entire SoC)
+   bit0: Asserts RESET1 (P0.0 = 0, PM0.0 = 0 (output)) but does NOT deassert it (wtf?). This seems to kill the entire SoC: is it because it doesn't deassert it, or does it not deassert it because the SoC hangs anyway? This is the pin that controls some security-critical regs like CFG9_BOOTENV!
    bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
 |-