SHA Registers: Difference between revisions
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== | == REG_SHA_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
| Line 32: | Line 32: | ||
|- | |- | ||
|3 | |3 | ||
| | | Endianess (0=Little endian, 1=Big endian) | ||
|- | |- | ||
|4 | |4 | ||
| ? | | ? Input related. Changes the hash completely | ||
|- | |- | ||
|5 | |5 | ||
| Line 53: | Line 53: | ||
== REG_SHA_OUT == | == REG_SHA_OUT == | ||
This reg contains the SHA* hash after the final round. | This reg contains the SHA* hash after the final round. | ||
== REG_SHA_IN == | |||
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed). | |||
Revision as of 21:49, 7 September 2014
Registers
| NAME | PHYSICAL ADDRESS | WIDTH |
|---|---|---|
| REG_SHA_CNT | 0x1000A000 | 4 |
| REG_SHA_DATASIZE | 0x1000A004 | 4 |
| REG_SHA_OUT | 0x1000A040 | 0x20 |
| REG_SHA_IN | 0x1000A080 | 0x40 |
REG_SHA_CNT
| Bits | Description |
|---|---|
| 0-1 | 0=Hash ready, 1=Normal, 2=Final Round |
| 3 | Endianess (0=Little endian, 1=Big endian) |
| 4 | ? Input related. Changes the hash completely |
| 5 | Mode (0=SHA256, 1=SHA1) |
| 16 | Enable |
| 17 | 1 when FIFO expects read/write |
REG_SHA_DATASIZE
This reg contains the total size of the data written to REG_SHA_IN.
REG_SHA_OUT
This reg contains the SHA* hash after the final round.
REG_SHA_IN
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).