CONFIG11 Registers: Difference between revisions
| Line 359: | Line 359: | ||
! Description | ! Description | ||
|- | |- | ||
| | | 0x01 | ||
| No | | No | ||
| Yes | | Yes | ||
| | | 0x01 | ||
| 1x | | 1x | ||
| 268MHz | | 268MHz | ||
|- | |- | ||
| | | 0x02 | ||
| No | | No | ||
| No | | No | ||
| | | 0x01 | ||
| 1x | | 1x | ||
| 268MHz | | 268MHz | ||
|- | |- | ||
| | | 0x05 | ||
| Yes | | Yes | ||
| Yes | | Yes | ||
| | | 0x03 | ||
| 3x | | 3x | ||
| 804MHz | | 804MHz | ||
|- | |- | ||
| | | 0x03 | ||
| Yes | | Yes | ||
| No | | No | ||
| | | 0x02 | ||
| 2x | | 2x | ||
| 536MHz (tested on New3DS) | | 536MHz (tested on New3DS) | ||
| Line 390: | Line 390: | ||
Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). | Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). | ||
The following | The following register value(s) were tested on New3DS by patching the kernel: | ||
* 0x0: Entire system hangs. | |||
* 0x2: Entire system hangs. | |||
* 0x3: ARM11 runs at 536MHz. | |||
* 0x4: Entire system hangs. | * 0x4: Entire system hangs. | ||
* 0x6: Entire system hangs. | * 0x6: Entire system hangs. | ||
* 0xD: Same result as 0x05. | |||
== PDN_MPCORE_CNT == | == PDN_MPCORE_CNT == | ||