Difference between revisions of "SHA Registers"

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!  Description
 
!  Description
 
|-
 
|-
| 0-1
+
| 0
| 0=Hash ready, 1=Normal, 2=Final Round
+
| Start (1=enable/busy, 0=idle)
 +
|-
 +
| 1
 +
| Pad input
 
|-
 
|-
 
| 2
 
| 2
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|-
 
|-
 
| 16
 
| 16
| Enable
+
| ?
 
|-
 
|-
 
| 17
 
| 17

Revision as of 02:24, 9 March 2016

Registers

Old3DS Name Address Width Used by
Yes SHA_CNT 0x1000A000 4 Boot9, Process9
Yes SHA_BLKCNT 0x1000A004 4 Process9
Yes SHA_HASH 0x1000A040 0x20 Process9
Yes SHA_INFIFO 0x1000A080 0x40 Boot9, Process9

SHA_CNT

Bits Description
0 Start (1=enable/busy, 0=idle)
1 Pad input
2 ?
3 Output Endianess (0=Little endian, 1=Big endian)
4-5 Mode (0=SHA256, 1=SHA224, 2=3=SHA1)
6 ?
7 ?
8 Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO.
9 Unknown. This bit seems to be cleared by reading from SHA_INFIFO.
10 ?
16 ?
17 1 when FIFO expects read/write

SHA_BLKCNT

This reg contains the total size of the data written to REG_SHA_IN, this field is updated when performing hash-function final-round.

SHA_HASH

This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.

SHA_INFIFO

The data to be hashed must be written here. It does not matter what offset is written to.