SHA Registers: Difference between revisions
m →SHA_CNT |
|||
| Line 26: | Line 26: | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| [[# | | [[#SHA_FIFO|SHA_FIFO]] | ||
| 0x1000A080 | | 0x1000A080 | ||
| 0x40 | | 0x40 | ||
| Line 41: | Line 41: | ||
|- | |- | ||
| 1 | | 1 | ||
| | | Final round (1=enable/busy, 0=normal) | ||
|- | |- | ||
| 2 | | 2 | ||
| | | Enable IRQ 0 | ||
|- | |- | ||
| 3 | | 3 | ||
| Output Endianess (0= | | Output Endianess (0=little, 1=big) | ||
|- | |- | ||
| 4-5 | | 4-5 | ||
| Line 59: | Line 59: | ||
|- | |- | ||
| 8 | | 8 | ||
| | | Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO. | ||
|- | |- | ||
| 9 | | 9 | ||
| | | Enable FIFO (1=fifo, 0=write-only) | ||
|- | |- | ||
| 10 | | 10 | ||
| | | Enable IRQ 1 | ||
|- | |- | ||
| 16 | | 16 | ||
| Line 71: | Line 71: | ||
|- | |- | ||
| 17 | | 17 | ||
| | | ? | ||
|} | |} | ||
| Line 80: | Line 80: | ||
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register. | This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register. | ||
== | == SHA_FIFO == | ||
The data to be hashed must be written here. It does not matter what offset is written to. | The data to be hashed must be written here. It does not matter what offset is written to. | ||