SPI Registers: Difference between revisions

Revision as of 21:52, 20 April 2019 view source Profi200 (talk \| contribs) Trusted 137 edits m →SPI_NEW_DONE ← Older edit		Revision as of 21:54, 20 April 2019 view source Profi200 (talk \| contribs) Trusted 137 edits m →SPI_NEW_STATUS Newer edit →
Line 231:		Line 231:

	==SPI_NEW_STATUS==		==SPI_NEW_STATUS==
	Bit0: FIFO busy.		Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.