I2C Registers: Difference between revisions
mcu reset →Device 3 |
Free regs →Device 3 |
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bit2: reboot (used by mcu sysmodule and LgyBg) | bit2: reboot (used by mcu sysmodule and LgyBg) | ||
bit3: used by LgyBg to power off, causes hangs in 3DS-mode | bit3: used by LgyBg to power off, causes hangs in 3DS-mode | ||
bit4: | bit4: used by PTM to signal that sleep mode is about to be entered | ||
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F. | Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F. | ||
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Line 672: | Line 672: | ||
| ds | | ds | ||
| rw | | rw | ||
| | | Free register bank address select | ||
Selects the index to read from in the free register bank, up to 200 (?). Used with reg 0x61. | |||
Reading from this register | |||
Reading from this register seem to read N bytes from the bank while incrementing the internal index by the same amount. | |||
Byte 0: bit0 = "WirelessDisabled", bit1 = "SoftwareClosed", bit2 = "PowerOffInitiated", bit3 = "LgyNativeResolution", bit4 = "LegacyJumpProhibited" | |||
Byte 1: Legacy LCD data | |||
Bytes 2 and 3: Local Friend Code counter | |||
Bytes 4 and 5: UUID clock sequence | |||
Bytes 6 and 7: Unused | |||
Bytes 8 to 175: Play count data for legacy titles | |||
Bytes 176 to 199: Unused | |||
|- | |- | ||
| 0x61 | | 0x61 | ||
| ds(0x100) | | ds(0x100) | ||
| rw | | rw | ||
| | | Free register bank, data is read from/written to here. | ||
Writing to here seems to increment the internal index? | |||
|- | |- | ||
| 0x62 - 0x7E | | 0x62 - 0x7E |