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fix wiki links
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Offset
! Offset
| 0x108
| 0x108
| 2
| 2
| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are (u8*)(0x1EC40000 + bit position) (?).
| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]] and [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).
|-
|-
| 0x10C
| 0x10C
| 0x10F
| 0x10F
| 1
| 1
| Flags (bit0=?, bit1=load special segment)
| Flags:
bit0: if set, DSP module calls [[DSP:RecvData]] on all three registers and expects them to reply value 1
bit1: if set, load special segment
|-
|-
| 0x110
| 0x110
The normal ending of this files is *.cdc
The normal ending of this files is *.cdc
[[Category:File formats]]
[[Category:DSP]]