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→LCD Source Framebuffer Setup
== Map ==
== Map ==
Address mappings for the external registers. GSPGPU:WriteHWRegs takes these addresses relative to 0x1EB00000.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! User VA
! User VA
| ?
| ?
| Writes 0xFF2 on GPU init.
| Writes 0xFF2 on GPU init.
|-
| 0x1EF000C0
| 0x104000C0
| 4
| Backlight control
| Writes 0x0 to allow backlights to turn off, 0x20000000 to force them always on.
|-
|-
| 0x1EF00400
| 0x1EF00400
| 0x10400400
| 0x10400400
| 0x100
| 0x100
| [[#Framebuffer_Setup|Framebuffer Setup]] "PDC0" (top screen)
| [[#LCD Source Framebuffer Setup|Framebuffer Setup]] "PDC0" (top screen)
|
|
|-
|-
| 0x10400500
| 0x10400500
| 0x100
| 0x100
| [[#Framebuffer_Setup|Framebuffer Setup]] "PDC1" (bottom)
| [[#LCD Source Framebuffer Setup|Framebuffer Setup]] "PDC1" (bottom)
|
|
|-
|-
| [[#Transfer_Engine|Transfer Engine]] "DMA"
| [[#Transfer_Engine|Transfer Engine]] "DMA"
|
|
|-
|colspan="5"| 0x1EF01000/0x10401000 - 0x1EF01C00/0x10401C00 maps to [[GPU/Internal_Registers|GPU internal registers]]. These registers are usually not read/written directly here, but are written using the command list interface below (corresponding to the GPUREG_CMDBUF_* internal registers)
|-
|-
| 0x1EF01000
| 0x1EF01000
== LCD Source Framebuffer Setup ==
== LCD Source Framebuffer Setup ==
All of these registers must be accessed with 32bit operations regardless of the registers' actual bit size.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Offset
! Offset
! Name
! Name
! Comments
! Comments
|-
| 0x00
| Pixel clock
| Higher values are slower, 12bits.
Setting this value too low will make the screen not be able to sync any pixels other than a single one from the wrong location. The lowest the screen can handle is 0x1C2, at 0x1C1 the display loses a few scanlines worth of pixel clock (though not noticable).
|-
| 0x04
| HBlank timer(?)
| Seems to determine the horizontal blanking interval.
Setting this to lower than <code>HTotal - HDisp</code> will make the screen not catch up with the scanlines, some will be skipped, some will be misaligned.
Setting this to higher than <code>HTotal - HDisp</code> will make the displayed image misaligned to the right.
Setting this to higher than <code>HTotal</code> seems to make the horizontal synchronization never happen.
|-
| 0x08
| ?
| must be >= REG#0x00
|-
| 0x0C
| ?
| must be >= REG#0x08
|-
| 0x10
| Window X start (LgyFb)
| Offsets the viewing window on the display's physical X co-ordinate relative to its front porch end.
Outside of LgyFb changing this value only seems to cause weird pixel interpolation and blurryness.
|-
| 0x14
| Window X end (LgyFb)
| Window X start + window width - 1 is written here to set the end display scan pixel offset.
Outside of LgyFb it seems to offset the screen to the left if this value is high enough, but can glitch out the syncing on the bottom screen. High enough values will make the screen skip too many "pixels". If this value is higher or equal to *some value* (aka. if less than one pixel per line is displayed on the screen) then the screen will lose synchronization.
|-
| 0x18
| Window Y start (LgyFb)
| Offsets the viewing window on the display's physical Y co-ordinate relative to the first visible scanline.
|-
| 0x20
| Low: Window Y end (LgyFb)
High: ???
| Low: Window Y start + window height - 1 is written here to set the last display scanline relative to the first visible scanline.
High: This is cleared to zero when displaying LgyFb. Outside of LgyFb this doesn't really seem to do anything useful.
??? extra pixels get inserted in the first displayed scanline and thus the image gets shifted to the right. Seems to make horizontal syncing a bit glitchy. If a HSync occurs, the pixel data is suspended until the first pixel is supposed to be displayed, then the pixel stream will continue where it left off until a delayed HSync gets processed relative to the pixel data.
|-
| 0x24
| Low: ???
High: ???
| The low 12bit halfword seems to affect:
- the total amount of scanlines displayed
- vertical pixel data offset if the GPU can't VSync properly
- VSync length
|-
| 0x28
| VBlank timer(?)
| Seems to determine the vertical blanking interval.
Setting this to lower than <code>VTotal - VDisp</code> will cut off the top <code>VTotal - VDisp - thisvalue</code> lines.
Setting this to higher than <code>VTotal - VDisp</code> will make the image be pushed downwards with the overscan color visible.
Setting this to higher than <code>HTotal</code> will make the GPU skip vertical pixel data synchronization (hence filling the screen with the rest of the pixel data past the given screen framebuffer size). Also will skip <code>thisvalue + somevalue - HTotal</code> lines into the "global" pixel buffer.
|-
| 0x30
| VTotal
| Total amount of vertical scanlines in the pixel buffer, must be bigger than *an unknown blanking-like value*. If this value is less than VDisp then the last two scanlines will be repeated interlaced until VDisp is reached.
|-
| 0x34
| VDisp(?)
| Total amonut of vertical scanlines displayed (only for top screen it seems like). If this value is less than VTotal then the rest of the scanlines will not be updated on the screen, so those will slowly fade out. Must be bigger than *an unknown blanking-like value*, otherwise an underflow will happen.
|-
| 0x38
| Vertical data offset(?)
| ??? Seems to offset the screen upwards if this value is high enough. If this value is higher or equal to *some value* (aka. if less than one scanline is displayed on the screen) then the screen will lose synchronization.
|-
| 0x44
| ???
| similar functionality to 0x10
|-
| 0x48
| ???
| bit0 seems to disable HSync, bit8 seems to disable VSync, rest of the bits aren't writable.
|-
| 0x4C
| Overscan filler color
|
|-
| 0x50
| Horizontal position counter
| read-only
|-
| 0x54
| Horizontal scanline (HBlank) counter
| read-only
|-
|-
| 0x5C
| 0x5C
| 4
| ???
| Framebuffer width & height
| low u16: framebuffer width
| Lower 16 bits: width, upper 16 bits: height
high u16: framebuffer height??? (seems to be unused)
|-
| 0x60
| ???
| low u16: timing data(?)
high u16: framebuffer total width (amount of pixels blitted regardless of framebuffer width)
|-
| 0x64
| ???
| low u16: unknown
high u16: framebuffer total height (amount of scanlines blitted regardless of framebuffer height)
|-
|-
| 0x68
| 0x68
| Framebuffer A first address
| Framebuffer A first address
| For top screen, this is the left eye 3D framebuffer.
| For top screen, this is the left eye 3D framebuffer.
|-
|-
| 0x6C
| 0x6C
| Framebuffer A second address
| Framebuffer A second address
| For top screen, this is the left eye 3D framebuffer.
| For top screen, this is the left eye 3D framebuffer.
|-
|-
| 0x70
| 0x70
| Framebuffer format
| Framebuffer format
| Bit0-15: framebuffer format, bit16-31: unknown
| Bit0-15: framebuffer format, bit16-31: unknown
|-
|-
| 0x78
| 0x78
| Framebuffer select
| Framebuffer select
| Bit0: which framebuffer to display, bit1-7: unknown
| Bit0: which framebuffer to display, bit1-7: unknown
|-
| 0x80
| Color lookup table index select
| 8bits, write-only
|-
| 0x84
| Color lookup table indexed element
| Contains the value of the color lookup table indexed by the above register, 24bits, RGB8 (0x00BBGGRR)
Accessing this register will increase the index register by one
|-
|-
| 0x90
| 0x90
| Framebuffer stride
| Framebuffer stride
| Distance in bytes between the start of two framebuffer rows (must be a multiple of 8).
| Distance in bytes between the start of two framebuffer rows (must be a multiple of 8).
|-
|-
| 0x94
| 0x94
| Framebuffer B first address
| Framebuffer B first address
| For top screen, this is the right eye 3D framebuffer. Unused for bottom screen.
| For top screen, this is the right eye 3D framebuffer. Unused for bottom screen.
|-
|-
| 0x98
| 0x98
| Framebuffer B second address
| Framebuffer B second address
| For top screen, this is the right eye 3D framebuffer. Unused for bottom screen.
| For top screen, this is the right eye 3D framebuffer. Unused for bottom screen.
| 0x1EF00C18
| 0x1EF00C18
| Setting bit0 starts the transfer. Upon completion, bit0 is unset and bit8 is set.
| Setting bit0 starts the transfer. Upon completion, bit0 is unset and bit8 is set.
|-
| 0x1EF00C1C
| ?
|-
|-
| 0x1EF00C20
| 0x1EF00C20
|-
|-
| 0x1EF00C24
| 0x1EF00C24
| TextureCopy input line width (bits 0-15) and gap (bits 16-31), in bytes.
| TextureCopy input line width (bits 0-15) and gap (bits 16-31), in 16 byte units.
|-
|-
| 0x1EF00C28
| 0x1EF00C28
|-
|-
| 16
| 16
| Use some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
| Use 32x32 block tiling mode, instead of the usual 8x8 one. Output dimensions must be multiples of 32, even if cropping with bit 2 set above.
|-
|-
| 17-23
| 17-23
=== TextureCopy ===
=== TextureCopy ===
When bit 3 of the control register is set, the hardware performs a TextureCopy-mode transfer. In this mode, all other bits of the control register (except for bit 2, which still needs to be set correctly) and the regular dimension registers are ignored, and no format conversions are done. Instead, it performs a raw data copy from the source to the destination, but with a configurable gap between lines. The total amount of bytes to copy is specified in the size register, and the hardware loops reading lines from the input and writing them to the output until this amount is copied. The "gap" specified in the input/output dimension register is the number of bytes to skip after each "width" bytes of the input/output, and is NOT counted towards the total size of the transfer.
When bit 3 of the control register is set, the hardware performs a TextureCopy-mode transfer. In this mode, all other bits of the control register (except for bit 2, which still needs to be set correctly) and the regular dimension registers are ignored, and no format conversions are done. Instead, it performs a raw data copy from the source to the destination, but with a configurable gap between lines. The total amount of bytes to copy is specified in the size register, and the hardware loops reading lines from the input and writing them to the output until this amount is copied. The "gap" specified in the input/output dimension register is the number of chunks to skip after each "width" chunks of the input/output, and is NOT counted towards the total size of the transfer.
By correctly calculating the input and output gap sizes it is possible to use this functionality to copy arbitrary sub-rectangles between differently-sized framebuffers or textures, which is one of its main uses over a regular no-conversion DisplayTransfer. When copying tiled textures/framebuffers it's important to remember that the contents of a tile are laid out sequentially in memory, and so this should be taken into account when calculating the transfer parameters.
By correctly calculating the input and output gap sizes it is possible to use this functionality to copy arbitrary sub-rectangles between differently-sized framebuffers or textures, which is one of its main uses over a regular no-conversion DisplayTransfer. When copying tiled textures/framebuffers it's important to remember that the contents of a tile are laid out sequentially in memory, and so this should be taken into account when calculating the transfer parameters.
|}
|}
These 3 registers are used by [[GSP_Shared_Memory|GX command]] 1. This is used for [[GPU_Commands|GPU commands]].
These 3 registers are used by [[GSP_Shared_Memory|GX command]] 1. This is used for [[GPU/Internal_Registers|GPU commands]].
== Framebuffers ==
== Framebuffers ==