User contributions
7 May 2019
SPI Registers
Registers: Use same naming scheme as NDMA
-104
SPI Registers
SPI_NEW_CNT
m+24
SPI Registers
Registers
+906
CONFIG11 Registers
Registers
mCONFIG9 Registers
CFG9_CARDCTL
m+33
28 April 2019
20 April 2019
SPI Registers
SPI_NEW_STATUS
m+60
SPI Registers
SPI_NEW_DONE
m+90
SPI Registers
SPI_NEW_CNT
m+12
ARM11 Interrupts
Hardware Interrupts
m+27
29 May 2018
28 May 2018
CONFIG9 Registers
CFG9_SDSLOTCTL
m+15
CONFIG9 Registers
CFG9_SDSLOTCTL
m+13
CONFIG9 Registers
CFG9_SDSLOTCTL
m+55
CONFIG9 Registers
no edit summary
+367
20 May 2018
15 May 2018
19 April 2018
30 December 2017
CONFIG11 Registers
CFG11_MPCORE_CNT
m+96
CONFIG11 Registers
CFG11_MPCORE_CNT: Core 3 powers on even with bit 0 unset.
m-62
CONFIG11 Registers
CFG11_MPCORE_CLKCNT
m+42
17 December 2017
30 June 2017
GPU/External Registers
Transfer Engine
m+1
GPU/External Registers
Transfer Engine
m+30
ARM11 Interrupts
Hardware Interrupts: Confirmed
m+2
29 June 2017
23 June 2017
28 January 2017
27 September 2016
23 September 2016
Homebrew Applications
Emulators: Fuuuu
m-5
Homebrew Applications
Emulators: Changed link to downloads page.
m+5
17 July 2016
User talk:Windwakr
no edit summary
m+29
User talk:Windwakr
no edit summary
+48
User talk:Windwakr
no edit summary
m+9
User talk:Windwakr
Created page with "My god dude. Look at the fifo count fields in AES_CNT."
16 July 2016
AES Registers
AES_WRFIFO/AES_RDFIFO: Too inaccurate.
m+149
AES Registers
Thanks to martin from gbatek for figuring this out!
m+114