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edits
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→Registers
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SHA_INFIFO|SHA_INFIFO]]
| [[#SHA_FIFO|SHA_FIFO]]
| 0x1000A080
| 0x1000A080
| 0x40
| 0x40
|-
|-
| 1
| 1
| Pad input/final round
| Final round (1=enable/busy, 0=normal)
|-
|-
| 2
| 2
| ?
| Enable IRQ 0
|-
|-
| 3
| 3
| Output Endianess (0=Little endian, 1=Big endian)
| Output Endianess (0=little, 1=big)
|-
|-
| 4-5
| 4-5
|-
|-
| 8
| 8
| Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO.
| Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO.
|-
|-
| 9
| 9
| Unknown. This bit seems to be cleared by reading from SHA_INFIFO.
| Enable FIFO (1=fifo, 0=write-only)
|-
|-
| 10
| 10
| ?
| Enable IRQ 1
|-
|-
| 16
| 16
|-
|-
| 17
| 17
| 1 when FIFO expects read/write
| ?
|}
|}
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.
== SHA_INFIFO ==
== SHA_FIFO ==
The data to be hashed must be written here. It does not matter what offset is written to.
The data to be hashed must be written here. It does not matter what offset is written to.