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393 bytes added ,  14:51, 29 January 2021
sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
uint8_t flags; // @2 bit0: DST_CFGSRC_IS_PERIPHERAL, bit1: SRC_CFGDST_IS_PERIPHERAL, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: DST_ALT_CFGSRC_IS_RAM, bit7: SRC_ALT_CFGDST_IS_RAM
uint8_t padding;
DmaSubConfig dst_cfg;
struct DmaSubConfig {
sint8_t peripheral_id; // @0 If not *_ALT_CFG _IS_RAM set, this must be < 0x1E. uint8_t burst_size_rawallowed_burst_sizes; // (1 << raw size) bytes, bit4 is ignored? // @1 Accepted values: 4=fixed_addr??, 8, 4|8=increment_addr??12, 121|2|4|8 =lgy_fb_copy?, 15=userspace_copy? (??) sint16_t max_burst_size_bitsgather_granule_size; // @2 Must be 0 or multiple of 4? sint16_t transfer_size?gather_stride; // @4 Must Has to be >= 0, must not be 0 if peripheral_id == 0xFF. sint16_t unk4scatter_granule_size; // @6 sint16_t transfer_stride?scatter_stride; // @8Can be negative.
}
If SRC_CFGSRC_IS_PERIPHERAL/DST_CFG SRC_IS_PERIPHERAL is set in the flags field, the configuration for src/dst is loaded from src_cfg/dst_cfg respectivelyand the transfer will be done from/to a fixed address. If the *_ALT_CFG _IS_RAM flag is set same thing goes, except byte0 of each cfg is forced to 0xFF(RAM) and the transfer will be done from/to an incrementing address. ALT_CFG *_IS_RAM has priority over CFG_IS_PERIPHERAL.
If CFG neither *_IS_PERIPHERAL or ALT_CFG *_IS_RAM is not set, default configuration is loaded:
.peripheral_id = 0xFF,
.unk2 allowed_burst_sizes = 0xF1 | 2 | 4 | 8, .unk3 gather_granule_size = 0x80, .transfer_size gather_stride = 0, .unk4 scatter_granule_size = 0x80, .unk5 scatter_stride = 0, Checks suggest that unk2 of DmaSubConfig equalling 4 means NO_INCREMENT (don't increment after read/write).
If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.
|-
| 0x12
| mvd(y2r2)| ?SetSendingY
|-
| 0x13
| mvd(y2r2)| ?SetSendingU
|-
| 0x14
| mvd(y2r2)| ?SetSendingV
|-
| 0x15
| mvd(y2r2)| ?SetSendingYUV
|-
| 0x16
| mvd(y2r2)| ?SetReceiving
|-
| 0x17
| mvd
| ?Related to l2b
|-
| 0x18
| mvd
| ?Related to l2b
|-
| 0x19
| mvd
| ?Related to l2b
|-
| 0x1A
| mvd
| ?Related to l2b
|}
! Description
|-
| 0 (?)
| Process9
| CTRCARDCTRCARD1 (0x10004000?)|-| 1| ?| CTRCARD2 (0x10005000?)|-| 2| ?| TMIO1 (0x10006000)|-| 3| ?| TMIO3 (0x10007000)|-| 4| ?| AES in|-| 5| ?| AES out|-| 6| ?| SHA in
|-
| 7
| Process9
| SHAout
|-
|}
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