Line 7:
Line 7:
sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
−
uint8_t flags; // @2 bit0: DST_IS_PERIPHERAL, bit1: SRC_IS_PERIPHERAL, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: DST_IS_RAM, bit7: SRC_IS_RAM
+
uint8_t flags; // @2 bit0: SRC_IS_PERIPHERAL, bit1: DST_IS_PERIPHERAL, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: SRC_IS_RAM, bit7: DST_IS_RAM
uint8_t padding;
uint8_t padding;
DmaSubConfig dst_cfg;
DmaSubConfig dst_cfg;
Line 16:
Line 16:
sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.
sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.
uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4|8 = 12, 1|2|4|8 = 15
uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4|8 = 12, 1|2|4|8 = 15
−
sint16_t max_burst_total; // @2 Burst length * burst size
+
sint16_t gather_granule_size; // @2
−
sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.
+
sint16_t gather_stride; // @4 Has to be >= 0, must not be 0 if peripheral_id == 0xFF.
−
sint16_t unk4; // @6
+
sint16_t scatter_granule_size; // @6
−
sint16_t transfer_stride?; // @8
+
sint16_t scatter_stride; // @8 Can be negative.
}
}
Line 28:
Line 28:
.peripheral_id = 0xFF,
.peripheral_id = 0xFF,
.allowed_burst_sizes = 1 | 2 | 4 | 8,
.allowed_burst_sizes = 1 | 2 | 4 | 8,
−
.max_burst_total = 0x80,
+
.gather_granule_size = 0x80,
−
.transfer_size? = 0,
+
.gather_stride = 0,
−
.unk4 = 0x80,
+
.scatter_granule_size = 0x80,
−
.transfer_stride? = 0,
+
.scatter_stride = 0,
If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.
If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.
Line 93:
Line 93:
|-
|-
| 0x12
| 0x12
−
| mvd
+
| mvd (y2r2)
−
| ?
+
| SetSendingY
|-
|-
| 0x13
| 0x13
−
| mvd
+
| mvd (y2r2)
−
| ?
+
| SetSendingU
|-
|-
| 0x14
| 0x14
−
| mvd
+
| mvd (y2r2)
−
| ?
+
| SetSendingV
|-
|-
| 0x15
| 0x15
−
| mvd
+
| mvd (y2r2)
−
| ?
+
| SetSendingYUV
|-
|-
| 0x16
| 0x16
−
| mvd
+
| mvd (y2r2)
−
| ?
+
| SetReceiving
|-
|-
| 0x17
| 0x17
| mvd
| mvd
−
| ?
+
| Related to l2b
|-
|-
| 0x18
| 0x18
| mvd
| mvd
−
| ?
+
| Related to l2b
|-
|-
| 0x19
| 0x19
| mvd
| mvd
−
| ?
+
| Related to l2b
|-
|-
| 0x1A
| 0x1A
| mvd
| mvd
−
| ?
+
| Related to l2b
|}
|}
Line 138:
Line 138:
| 0
| 0
| Process9
| Process9
−
| CTRCARD
+
| CTRCARD1 (0x10004000?)
+
|-
+
| 1
+
| ?
+
| CTRCARD2 (0x10005000?)
+
|-
+
| 2
+
| ?
+
| TMIO1 (0x10006000)
+
|-
+
| 3
+
| ?
+
| TMIO3 (0x10007000)
+
|-
+
| 4
+
| ?
+
| AES in
+
|-
+
| 5
+
| ?
+
| AES out
+
|-
+
| 6
+
| ?
+
| SHA in
|-
|-
| 7
| 7
| Process9
| Process9
−
| SHA
+
| SHA out
|-
|-
|}
|}