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I2C Registers: Difference between revisions

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   rw = read-write
   rw = read-write
   wo = write-only (reading will yield 00, FF, or unpredictable data)
   wo = write-only (reading will yield 00, FF, or unpredictable data)
  d* = dynamic register (explaination below this table)
   s* = shared register (explaination below this table)
   s* = shared register (explaination below this table)
  ds = dynamic shared (explaination below this table)
   *v = volatile (survives reboots)
   *v = volatile (survives reboots)
{| class="wikitable" border="1"
{| class="wikitable" border="1"
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|-
|-
| 0x02
| 0x02
| s
| d
| ro
| wo
| ?
| 2bit value, writing will mask away/"acknowledge" the event, set to 3 by mcuMainLoop on reset if reset source is Watchdog
  bit0: RTC clock value got reset to defaults
  bit1: Watchdog reset happened
|-
|-
| 0x03
| 0x03
| s
| ds
| rw
| rw
| Top screen flicker
| Top screen flicker
|-
|-
| 0x04
| 0x04
| s
| ds
| rw
| rw
| Bottom screen flicker
| Bottom screen flicker
Line 265: Line 270:
| 0x05
| 0x05
- 0x07
- 0x07
| s(3)
| s
| rw
| rw
| Danger zone - [[MCU_Services#MCU_firmware_versions|MCU unlock sequence]] is written here
| Danger zone - [[MCU_Services#MCU_firmware_versions|MCU unlock sequence]] is written here.
|-
|-
| 0x08
| 0x08
Line 389: Line 394:
|-
|-
| 0x20
| 0x20
| s
| d
| wo
| wo
| System power control:
| System power control:
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   bit2: reboot (used by mcu sysmodule and LgyBg)
   bit2: reboot (used by mcu sysmodule and LgyBg)
   bit3: used by LgyBg to power off, causes hangs in 3DS-mode
   bit3: used by LgyBg to power off, causes hangs in 3DS-mode
   bit4: doesn't seem to do anything, but an mcu::RTC command uses this
   bit4: an mcu::RTC command uses this, seems to do something with the watchdog
Other bits are unused, and seem to do nothing.
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.  
|-
|-
| 0x21
| 0x21
| s
| d
| ro(?)
| wo
| ?
| ??? switches up input bits from <code>0123456--</code> to <code>12-0435-</code> then writes them to REG[0x5D] (<code>0xFFC02</code>)
|-
|-
| 0x22
| 0x22
| s
| d
| wo
| wo
| Used to set LCD states
| Used to set LCD states
Line 415: Line 420:
   bit5: top screen backlight on
   bit5: top screen backlight on


bits 4 and 5 have no effect on a 2DS because the backlight source is the bottom screen
Bits 4 and 5 have no effect on a 2DS because the backlight source is the bottom screen.
The rest of the bits are masked away.
|-
|-
| 0x23
| 0x23
| s
| ??
| ro(?)
| wo
| ?
| ??? Seems to be stubbed, just returns the written value from the write handler function.
|-
|-
| 0x24
| 0x24
| s
| s
| ??
| rw
| Watchdog timer. This must be set *before* the timer is triggered, otherwise the old value is used. Value zero disables the watchdog.
| Watchdog timer. This must be set *before* the timer is triggered, otherwise the old value is used. Value zero disables the watchdog.
|-
|-
Line 438: Line 444:
|-
|-
| 0x27
| 0x27
| s
| sd
| ro
| rw
| Raw volume slider state
| Raw volume slider state
|-
|-
Line 448: Line 454:
|-
|-
| 0x29
| 0x29
| ds(0x64)
| sd(5)
| ro / rw
| rw
| Empty battery pattern holder, repeats all written bytes
| Power LED state + some extra data
|-
|-
| 0x2A
| 0x2A
Line 460: Line 466:
| s
| s
| rw
| rw
| Camera LED state, 0, 3, 6-0xF = off, 1 = slowly blinking, 2 = constantly on, 4 = flash once, 5 = delay before changing to 2
| Camera LED state, 4bits wide,
  0, 3, 6-0xF = off
  1 = slowly blinking
  2 = constantly on
  4 = flash once
  5 = delay before changing to 2
|-
|-
| 0x2C
| 0x2C
Line 479: Line 490:
| 0x2F
| 0x2F
| s
| s
| ro(?)
| wo?
| ?
| ??? The write function for this register is stubbed.
|-
|-
| 0x30
| 0x30
Line 506: Line 517:
|-
|-
| 0x3B
| 0x3B
- 0x3D
| s
| s
| rw
| rw
| Register 0x3B could be used to upload [[MCU_Services#MCU_firmware_versions|MCU firmware]] if some conditions are met.
| Register 0x3B could be used to upload [[MCU_Services#MCU_firmware_versions|MCU firmware]] if some conditions are met.
|-
| 0x3C
| s
| ro
| ???
|-
|-
| 0x3D
| 0x3D
Line 520: Line 535:
| s
| s
| wo
| wo
| Register-mapped MCU RESET?
| 2 bits
  bit0: turns off P00 and sets it to output mode (seems to kill the entire SoC)
  bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
|-
|-
| 0x40
| 0x40
Line 535: Line 552:
| s
| s
| rw
| rw
| ?
| Unused?
|-
|-
| 0x43
| 0x43
| s
| s
| rw
| rw
| ???, accelometer related
| Unused???, accelometer related
|-
|-
| 0x44
| 0x44
Line 580: Line 597:
|-
|-
| 0x4C
| 0x4C
| s
0x4E
| rw
| ?
|-
| 0x4D
| s
| rw
| ?
|-
| 0x4E
| s
| s
| rw
| rw
Line 635: Line 643:
- 0x5F
- 0x5F
| s
| s
| ro(?)
| -
| ? (these seem to be invalid regsiters)
| These registers are out of bounds (0xFFC00 and up), they don't exist, writing is no-op, reading will yield FFs.
|-
|-
| 0x60
| 0x60
Line 654: Line 662:
| 0x62 - 0x7E
| 0x62 - 0x7E
| s
| s
| invalid (ro)
| -
| These registers don't exist at all, thus reading them will yield 0xFF
| These registers don't exist, writing is no-op, reading will yield FFs.
|-
|-
| 0x7F
| 0x7F
Line 680: Line 688:
- 0xFF
- 0xFF
| s
| s
| invalid (ro)
| -
| These registers don't exist at all, thus reading them will yield 0xFF
| These registers don't exist, writing is no-op, reading will yield FFs.
|}
|}


Note: the letter "s" in the size field means that the given register is in a "shared register pool", meaning if you read/write with size more than 1 you can read the next `readamount-1` of shared registers. It's possible to corrupt the shared value of a "non-shared" register by writing into a shared register with a size bigger than one. Writing more than 0x100 bytes into a shared register will corrupt all writable registers, including the shared portion of "non-shared" registers.
Shared register: the letter "s" means that the given register is in a "shared register pool", meaning the resgister is in the register pool in RAM at address <code>0xFFBA4 + registernumber</code>.
 
Dynamic register: these registers aren't in the shared pool, they just "pretend" to be there. These registers often don't retain their set value, change rapidly, or control various hardware.


Non-shared register: it's a register separate from the shared register pool. Messing with these registers will not affect the shared register pool at all.
Non-shared (dynamic) register: it's a register whose contents separate from the shared register pool. Messing with these registers will not affect the shared register pool at all.


== Device 5 & 6 ==
== Device 5 & 6 ==
Retrieved from "https://www.3dbrew.org/wiki/I2C_Registers"