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834 bytes added ,  07:32, 18 February 2018
rw = read-write
wo = write-only (reading will yield 00, FF, or unpredictable data)
 
d* = dynamic register (explaination below this table)
s* = shared register (explaination below this table)
ds = dynamic shared (explaination below this table)
*v = volatile (survives reboots)
{| class="wikitable" border="1"
|-
| 0x02
| sd| rowo| ?2bit value, writing will mask away/"acknowledge" the event, set to 3 by mcuMainLoop on reset if reset source is Watchdog bit0: RTC clock value got reset to defaults bit1: Watchdog reset happened
|-
| 0x03
| sds
| rw
| Top screen flicker
|-
| 0x04
| sds
| rw
| Bottom screen flicker
| 0x05
- 0x07
| s(3)
| rw
| Danger zone - [[MCU_Services#MCU_firmware_versions|MCU unlock sequence]] is written here.
|-
| 0x08
|-
| 0x20
| sd
| wo
| System power control:
bit2: reboot (used by mcu sysmodule and LgyBg)
bit3: used by LgyBg to power off, causes hangs in 3DS-mode
bit4: doesn't seem to do anything, but an mcu::RTC command uses thisOther bits are unused, and seem seems to do nothingsomething with the watchdogBit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
|-
| 0x21
| sd| ro(?)wo| ??? switches up input bits from <code>0123456--</code> to <code>12-0435-</code> then writes them to REG[0x5D] (<code>0xFFC02</code>)
|-
| 0x22
| sd
| wo
| Used to set LCD states
bit5: top screen backlight on
bits Bits 4 and 5 have no effect on a 2DS because the backlight source is the bottom screen.The rest of the bits are masked away.
|-
| 0x23
| s??| ro(?)wo| ??? Seems to be stubbed, just returns the written value from the write handler function.
|-
| 0x24
| s
| ??rw
| Watchdog timer. This must be set *before* the timer is triggered, otherwise the old value is used. Value zero disables the watchdog.
|-
|-
| 0x27
| ssd| rorw
| Raw volume slider state
|-
|-
| 0x29
| dssd(0x645)| ro / rw| Empty battery pattern holder, repeats all written bytesPower LED state + some extra data
|-
| 0x2A
| s
| rw
| Camera LED state, 4bits wide, 0, 3, 6-0xF = off, 1 = slowly blinking, 2 = constantly on, 4 = flash once, 5 = delay before changing to 2
|-
| 0x2C
| 0x2F
| s
| ro(wo?)| ??? The write function for this register is stubbed.
|-
| 0x30
|-
| 0x3B
- 0x3D
| s
| rw
| Register 0x3B could be used to upload [[MCU_Services#MCU_firmware_versions|MCU firmware]] if some conditions are met.
|-
| 0x3C
| s
| ro
| ???
|-
| 0x3D
| s
| wo
| Register-mapped MCU RESET?2 bits bit0: turns off P00 and sets it to output mode (seems to kill the entire SoC) bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
|-
| 0x40
| s
| rw
| Unused?
|-
| 0x43
| s
| rw
| Unused???, accelometer related
|-
| 0x44
|-
| 0x4C
| s| rw| ?|-| 0x4D| s| rw| ?|-| 0x4E
| s
| rw
- 0x5F
| s
| ro(?)- | ? These registers are out of bounds (these seem to be invalid regsiters0xFFC00 and up), they don't exist, writing is no-op, reading will yield FFs.
|-
| 0x60
| 0x62 - 0x7E
| s
| invalid (ro)-| These registers don't exist at all, thus writing is no-op, reading them will yield 0xFFFFs.
|-
| 0x7F
- 0xFF
| s
| invalid (ro)-| These registers don't exist at all, thus writing is no-op, reading them will yield 0xFFFFs.
|}
NoteShared register: the letter "s" in the size field means that the given register is in a "shared register pool", meaning if you read/write with size more than 1 you can read the next `readamount-1` of shared registers. It's possible to corrupt resgister is in the shared value of a "non-shared" register by writing into a shared register with a size bigger than onepool in RAM at address <code>0xFFBA4 + registernumber</code>. Writing more than 0x100 bytes into a shared  Dynamic register will corrupt all writable : these registers, including aren't in the shared portion of pool, they just "non-sharedpretend" to be there. These registersoften don't retain their set value, change rapidly, or control various hardware.
Non-shared (dynamic) register: it's a register whose contents separate from the shared register pool. Messing with these registers will not affect the shared register pool at all.
== Device 5 & 6 ==
188

edits

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