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And the TP to get Clock, Vertical-Sync and Horizontal-Sync.
And the TP to get Clock, Vertical-Sync and Horizontal-Sync.
== Captured Video Control Signals ==
The following picutres show plots of the control signals CLK (TP189), HSYNC (TP190) and VSYNC (TP191). The used sample rate were 50MHz.
The full plot shows about 2.6ms.
[[File:Stp_PCLK_VSYNC_HSYNC_full.jpg|1200px]]
This plot shows 1.28us, mainly featuring the clock
[[File:Stp_PCLK_VSYNC_HSYNC_0..64.jpg|1200px]]
Setup
The signal capturing was done by using an DE10-NANO FPGA development board, Intel signal tap analyzer and 5 wires soldered to the TPs of an EU-O3DS (roughly 25cm long, parallel wired).
VCD and CVS files:
[[Media: Stp_PCLK_VSYNC_HSYNC.7z]]
(to view the VCD file use GTK Wave or similar programs).
== Links ==
== Links ==