533
edits
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→Device 3
Line 407:
Line 407:
| System power control:
| System power control:
bit0: power off
bit0: power off
− bit1: reboot (unused?)
+ bit1: full reboot (unused). Discards things like [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]]
− bit2: reboot (used by mcu sysmodule and LgyBg)
+ bit2: reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.
− bit3: used by LgyBg to power off, causes hangs in 3DS-mode
+ bit3: reset FCRAM (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also implements this function.
− bit4: used by PTM to signal that sleep mode is about to be entered
+ bit4: signal that sleep mode is about to be entered (used by PTM)
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
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Line 441:
Line 441:
| d
| d
| wo
| wo
−| Writing 0x72 ('r') resets the MCU, writing 0x77 ('w') resets its WDT. Seems to require special conditions, or doesn't work on current units
+| Writing 0x72 ('r') resets the MCU, but this is stubbed on retail?
|-
|-
| 0x24
| 0x24