215
edits
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Line 147:
Line 147: − + Line 154:
Line 154: − + − + − + − - Unknown synchronization/blanking (unknown where it happens)+ Line 175:
Line 175: − + − + − + + + + − + − + + + Line 308:
Line 313: − + − Bit 3: null (unwritable) − Bit 4-7: unknown − Bit 8-9: DMA size − Bit 10-15: null (unwritable) − Bit 16-31: unknown − − DMA sizes (in bytes): − 0 - 64 − 1 - 128 − 2 - 256 − 3 - ??? Line 375:
Line 369: − + − |- − | 3 − | ? Line 400:
Line 391: − + + + + + + + + − + − +
Update horizontal timing parameters (continuation)
All pixel and scanline timing values are 12bits, unless noted. This also applies to those fields where two u16 are combined into one register. Each u16 field is only 12bits in size. timin
All pixel and scanline timing values are 12bits, unless noted. This also applies to those fields where two u16 are combined into one register. Each u16 field is only 12bits in size. timin
The horizontal timing parameter order is as follows (values may overflow through xTotal register value):
The horizontal timing parameter order is as follows (values may overflow through HTotal register value):
0x10 < 0x14 <= 0x60.LO <= 0x04 <= 0x60.HI <= 0x08 <= 0x0C <= 0x10
0x10 < 0x14 <= 0x60.LO <= 0x04 <= 0x60.HI <= 0x08 <= 0x0C <= 0x10
0x18 <= 0x60.LO
0x18 <= 0x60.LO
There is an inherent latch order, where if two simultenaous events occur, one event wins over another.
There is an inherent latch order, where if two simultenaous events occur, one event wins over another.
Known latched modes (in no particular order):
Known latched modes (in order):
- HSync (triggers a line to the LCD to move to the next line)
- HSync (triggers a line to the LCD to move to the next line)
- Back porch (area between HSync and border being displayed, min 16 pixel clocks, otherwise the screen gets glitchy)
- Back porch (area between HSync and border being displayed, no pixels pushed, min 16 pixel clocks, otherwise the screen gets glitchy)
- Left border start (no image data is being displayed, just a configurable solid color)
- Left border start (no image data is being displayed, just a configurable solid color)
- Image start (pixel data is being DMA'd from video memory or main RAM)
- Image start (pixel data is being DMA'd from video memory or main RAM)
- Right border start/Image end (border color is being displayed after the main image)
- Right border start/Image end (border color is being displayed after the main image)
- Front porch (68 clock min, otherwise the screen doesn't sync properly, and really glitches out)
- Unknown synchronization (supposed to be probably right border end, but this mode seems to be broken or not do anything)
- Front porch (no pixels pushed, 68 clock min, otherwise the screen doesn't sync properly, and really glitches out)
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0x04
| 0x04
| HParam5
| HStart
|
| Determines when the image is going to be displayed in the visible region (register 0x60).
|-
|-
| 0x08
| 0x08
| HParam7
| HBR
| Right border start(?). Does nothing.
While this register seems to have no impact on the image whatsoever, it still has to be set to a valid value.
|
|
|-
|-
| 0x0C
| 0x0C
| HParam8
| HPF
|
| Front porch. The image is blanked during this period, and no pixels are pushed to the LCD.
Unknown why, but a single dot of red is displayed before entering this mode.
|-
|-
| 0x10
| 0x10
| 0x70
| 0x70
| Framebuffer format and other settings
| Framebuffer format and other settings
| Bit 0-2: framebuffer format
| See [[#Framebuffer_format|framebuffer format]]
|-
|-
| 0x74
| 0x74
|-
|-
| 2-0
| 2-0
| Color format
| [[#Framebuffer_color_formats|Color format]]
|-
|-
| 5-4
| 5-4
|-
|-
| 9-8
| 9-8
| Value 1 = unknown: get rid of rainbow strip on top of screen, 3 = unknown: black screen.
| DMA size
0 - 64 bytes
1 - 128 bytes
2 - 256 bytes
3 - ???
FCRAM doesn't support DMA size 3.
|-
|-
| 15-10
| 31-16
| Unused?
| Unknown
|}
|}