Bootloader: Difference between revisions

Line 101:

For an issue with console-unique key-init, see [[OTP_Registers|here]].

== Boot9 startup ==

0xffff0000 jumps to 0xffff8000. 0xffff8000 is crt0:

* Very first thing this does is clear u8 register 0x10000002 bit0 to zero.

* Then sp is initialized for each cpumode, IRQs/FIQs are disabled during the first mode-switch.

* Order of mode-switches + sp initialization: svc-mode = 0xfff04000, irq-mode = 0xfff03f00, system-mode = 0xfff03b00. Hence, the rest of the code following this runs in system-mode.

* Then L_ffff80cc/mpu_init() is called.

* Then L_ffff0038() is called, which initializes the exception-handler addresses @ 0x08000000.

* Then L_ffff81b8() is called(r4 + lr are saved on the DTCM stack), which after calling a memclear function which doesn't do anything, it then clears 0x08000030 size 0x10. Here the DTCM at 0xfff00000 size 0x4000 is cleared.

* Then L_ffff81b4() is called, which branches to DTCM_init(). This copies the initial DTCM data from the Boot9 data image into boot9, then it clears 0xFFF00230 - 0xFFF01AC0.

* Then LT_ffff8228/main is jumped to, with LR set to the address of an infinite-branch-loop instruction.

mpu_init():

* Bitmask 0x000f9005 is cleared in the cp15 control register. MCR instructions which do then following are then executed: flush entire instruction cache, flush entire data cache, and drain write buffer.

* Then the 8 [[Memory_layout|MPU]] memregions are initialized.

* ITCM memregion reg = 0x24: baseaddr=0x0, size = 128MB(0x08000000).

* DTCM memregion reg = 0xfff0000a: baseaddr=0xfff00000, size=16KB(0x00004000).

* Then instruction cachable and data cachable/bufferable bits for the MPU regions are setup.

* Then the instruction/data access permissions for the MPU regions are setup.

* Lastly bitmask 0x0005707d is orred in the cp15 control register.

== Boot Procedure ==

@@ Line 101: / Line 101: @@
 For an issue with console-unique key-init, see [[OTP_Registers|here]].
+== Boot9 startup ==
+xffff0000 jumps to 0xffff8000. 0xffff8000 is crt0:
+* Very first thing this does is clear u8 register 0x10000002 bit0 to zero.
+* Then sp is initialized for each cpumode, IRQs/FIQs are disabled during the first mode-switch.
+* Order of mode-switches + sp initialization: svc-mode = 0xfff04000, irq-mode = 0xfff03f00, system-mode = 0xfff03b00. Hence, the rest of the code following this runs in system-mode.
+* Then L_ffff80cc/mpu_init() is called.
+* Then L_ffff0038() is called, which initializes the exception-handler addresses @ 0x08000000.
+* Then L_ffff81b8() is called(r4 + lr are saved on the DTCM stack), which after calling a memclear function which doesn't do anything, it then clears 0x08000030 size 0x10. Here the DTCM at 0xfff00000 size 0x4000 is cleared.
+* Then L_ffff81b4() is called, which branches to DTCM_init(). This copies the initial DTCM data from the Boot9 data image into boot9, then it clears 0xFFF00230 - 0xFFF01AC0.
+* Then LT_ffff8228/main is jumped to, with LR set to the address of an infinite-branch-loop instruction.
+mpu_init():
+* Bitmask 0x000f9005 is cleared in the cp15 control register. MCR instructions which do then following are then executed: flush entire instruction cache, flush entire data cache, and drain write buffer.
+* Then the 8 [[Memory_layout|MPU]] memregions are initialized.
+* ITCM memregion reg = 0x24: baseaddr=0x0, size = 128MB(0x08000000).
+* DTCM memregion reg = 0xfff0000a: baseaddr=0xfff00000, size=16KB(0x00004000).
+* Then instruction cachable and data cachable/bufferable bits for the MPU regions are setup.
+* Then the instruction/data access permissions for the MPU regions are setup.
+* Lastly bitmask 0x0005707d is orred in the cp15 control register.
 == Boot Procedure ==