PDN Registers: Difference between revisions
Legacy regs |
LGR is what's written on the SoC in N3DS teardowns →PDN_MPCORE_SOCMODE |
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| Line 386: | Line 386: | ||
| 0-2 | | 0-2 | ||
| SoC mode. | | SoC mode. | ||
0=O3DS (2 cores, 256MHz) | Possible values: | ||
1=N3DS (4 cores, 256MHz), 5=N3DS (4 cores, 804MHz) | 0=O3DS (2 cores, 256MHz) | ||
2=N3DS prototype (2 cores, 256MHz), 3=N3DS prototype (2 cores, 536MHz) | 1=N3DS (LGR2?, 4 cores, 256MHz), 5=N3DS (LGR2?, 4 cores, 804MHz) | ||
2=N3DS prototype (LGR, 2 cores, 256MHz), 3=N3DS prototype (LGR, 2 cores, 536MHz) | |||
N3DS modes enable the New 3DS FCRAM extension and are needed to access N3DS-only devices. | N3DS modes enable the New 3DS FCRAM extension and are needed to access N3DS-only devices. | ||
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