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GPU/Internal Registers (edit)

Revision as of 05:09, 17 December 2014

15,390 bytes added ,  05:09, 17 December 2014
bunch of shader registers
Line 3,308: Line 3,308:     
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
 
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
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==== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ====
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 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
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| 0-3
 +
| Index of geometry shader input register which the 1st attribute will be stored in.
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|-
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| 4-7
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| Index of geometry shader input register which the 2nd attribute will be stored in.
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|-
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| 8-11
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| Index of geometry shader input register which the 3rd attribute will be stored in.
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|-
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| 12-15
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| Index of geometry shader input register which the 4th attribute will be stored in.
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|-
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| 16-19
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| Index of geometry shader input register which the 5th attribute will be stored in.
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|-
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| 20-23
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| Index of geometry shader input register which the 6th attribute will be stored in.
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|-
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| 24-27
 +
| Index of geometry shader input register which the 7th attribute will be stored in.
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|-
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| 28-31
 +
| Index of geometry shader input register which the 8th attribute will be stored in.
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|}
 +
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This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
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For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
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==== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ====
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{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of geometry shader input register which the 9th attribute will be stored in.
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|-
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| 4-7
 +
| Index of geometry shader input register which the 10th attribute will be stored in.
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|-
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| 8-11
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| Index of geometry shader input register which the 11th attribute will be stored in.
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|-
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| 12-15
 +
| Index of geometry shader input register which the 12th attribute will be stored in.
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|-
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| 16-19
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| Index of geometry shader input register which the 13th attribute will be stored in.
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|-
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| 20-23
 +
| Index of geometry shader input register which the 14th attribute will be stored in.
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|-
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| 24-27
 +
| Index of geometry shader input register which the 15th attribute will be stored in.
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|-
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| 28-31
 +
| Index of geometry shader input register which the 16th attribute will be stored in.
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|}
 +
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This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
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For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
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==== GPUREG_GSH_OUTMAP_MASK ====
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{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
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| 0
 +
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
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|-
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| 1
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| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
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|-
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| 2
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| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
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|-
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| 3
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| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
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|-
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| 4
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| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
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|-
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| 5
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| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
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|-
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| 6
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| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
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|}
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This register toggles the geometry shader unit's output registers.
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==== GPUREG_GSH_FLOATUNIFORM_CONFIG ====
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{| class="wikitable" border="1"
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! Bits
 +
! Description
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|-
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| 0-6
 +
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
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|-
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| 31
 +
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
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|}
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This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
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==== GPUREG_GSH_FLOATUNIFORM_DATA ====
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{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
 +
|}
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This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].
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* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
 +
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** first word : ZZWWWWWW
 +
** second word : YYYYZZZZ
 +
** third word : XXXXXXYY
 +
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* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
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=== GPUREG_GSH_CODE_CONFIG ===
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{| class="wikitable" border="1"
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! Bits
 +
! Description
 +
|-
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| 0-11
 +
| Target geometry shader code offset for data transfer.
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|}
 +
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This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]] should be written.
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NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
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=== GPUREG_GSH_CODE_DATA ===
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{| class="wikitable" border="1"
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! Bits
 +
! Description
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|-
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| 0-31
 +
| Geometry shader instruction data.
 +
|}
 +
 +
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODE_CONFIG|GPUREG_GSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
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=== GPUREG_GSH_OPDESCS_CONFIG ===
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{| class="wikitable" border="1"
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! Bits
 +
! Description
 +
|-
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| 0-6
 +
| Target geometry shader operand descriptor offset for data transfer.
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|}
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This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
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=== GPUREG_GSH_OPDESCS_DATA ===
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{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
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| 0-31
 +
| Geometry shader operand descriptor data.
 +
|}
 +
 +
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
    
=== Vertex shader registers ===
 
=== Vertex shader registers ===
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This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
 
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
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==== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ====
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 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of vertex shader input register which the 1st attribute will be stored in.
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|-
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| 4-7
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| Index of vertex shader input register which the 2nd attribute will be stored in.
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|-
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| 8-11
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| Index of vertex shader input register which the 3rd attribute will be stored in.
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|-
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| 12-15
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| Index of vertex shader input register which the 4th attribute will be stored in.
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|-
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| 16-19
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| Index of vertex shader input register which the 5th attribute will be stored in.
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|-
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| 20-23
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| Index of vertex shader input register which the 6th attribute will be stored in.
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|-
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| 24-27
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| Index of vertex shader input register which the 7th attribute will be stored in.
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|-
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| 28-31
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| Index of vertex shader input register which the 8th attribute will be stored in.
 +
|}
 +
 +
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
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For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.
 +
 +
==== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of vertex shader input register which the 9th attribute will be stored in.
 +
|-
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| 4-7
 +
| Index of vertex shader input register which the 10th attribute will be stored in.
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|-
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| 8-11
 +
| Index of vertex shader input register which the 11th attribute will be stored in.
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|-
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| 12-15
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| Index of vertex shader input register which the 12th attribute will be stored in.
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|-
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| 16-19
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| Index of vertex shader input register which the 13th attribute will be stored in.
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|-
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| 20-23
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| Index of vertex shader input register which the 14th attribute will be stored in.
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|-
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| 24-27
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| Index of vertex shader input register which the 15th attribute will be stored in.
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|-
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| 28-31
 +
| Index of vertex shader input register which the 16th attribute will be stored in.
 +
|}
 +
 +
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
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For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
 +
 +
==== GPUREG_VSH_OUTMAP_MASK ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0
 +
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
 +
|-
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| 1
 +
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
 +
|-
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| 2
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| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
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|-
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| 3
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| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
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|-
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| 4
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| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
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|-
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| 5
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| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
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|-
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| 6
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| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
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|-
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| 7
 +
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
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|-
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| 8
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| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
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|-
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| 9
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| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
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|-
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| 10
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| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
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|-
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| 11
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| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
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|-
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| 12
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| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
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|-
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| 13
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| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
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|-
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| 14
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| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
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|-
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| 15
 +
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
 +
|}
 +
 +
This register toggles the vertex shader units' output registers.
 +
 +
==== GPUREG_VSH_FLOATUNIFORM_CONFIG ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-6
 +
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
 +
|-
 +
| 31
 +
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
 +
|}
 +
 +
This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
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 +
==== GPUREG_VSH_FLOATUNIFORM_DATA ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
 +
|}
 +
 +
This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].
 +
 +
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
 +
 +
** first word : ZZWWWWWW
 +
** second word : YYYYZZZZ
 +
** third word : XXXXXXYY
 +
 +
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
 +
 +
=== GPUREG_VSH_CODE_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-11
 +
| Target vertex shader code offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]] should be written.
 +
 +
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
 +
 +
=== GPUREG_VSH_CODE_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-11
 +
| Target vertex shader code offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]] should be written.
 +
 +
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
 +
 +
=== GPUREG_VSH_CODE_DATA ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Vertex shader instruction data.
 +
|}
 +
 +
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODE_CONFIG|GPUREG_VSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
 +
 +
=== GPUREG_VSH_OPDESCS_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-6
 +
| Target vertex shader operand descriptor offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.
 +
 +
=== GPUREG_VSH_OPDESCS_DATA ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Vertex shader operand descriptor data.
 +
|}
 +
 +
This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
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