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formatting fix
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
=== GPUREG_GSH_CODE_CONFIG ===
==== GPUREG_GSH_CODE_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
=== GPUREG_GSH_CODE_DATA ===
==== GPUREG_GSH_CODE_DATA ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODE_CONFIG|GPUREG_GSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODE_CONFIG|GPUREG_GSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
=== GPUREG_GSH_OPDESCS_CONFIG ===
==== GPUREG_GSH_OPDESCS_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
=== GPUREG_GSH_OPDESCS_DATA ===
==== GPUREG_GSH_OPDESCS_DATA ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
=== GPUREG_VSH_CODE_CONFIG ===
==== GPUREG_VSH_CODE_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
=== GPUREG_VSH_CODE_CONFIG ===
==== GPUREG_VSH_CODE_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
=== GPUREG_VSH_CODE_DATA ===
==== GPUREG_VSH_CODE_DATA ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODE_CONFIG|GPUREG_VSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODE_CONFIG|GPUREG_VSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
=== GPUREG_VSH_OPDESCS_CONFIG ===
==== GPUREG_VSH_OPDESCS_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.
=== GPUREG_VSH_OPDESCS_DATA ===
==== GPUREG_VSH_OPDESCS_DATA ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"